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7617378 |
Multiprocessor system with retry-less TLBI protocol
A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each...
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7617366 |
Method and apparatus for filtering snoop requests using mulitiple snoop caches
A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have...
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7617329 |
Programmable protocol to support coherent and non-coherent transactions in a multinode system
A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol...
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7613885 |
Cache coherency control method, chipset, and multi-processor system
In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for...
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7613884 |
Multiprocessor system and method ensuring coherency between a main memory and a cache memory
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a...
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7606978 |
Multi-node computer system implementing global access state dependent transactions
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to...
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7606971 |
Storage control apparatus and external storage apparatus
A storage control apparatus includes a plurality of temporary storage units that are managed in a redundant manner by data mirroring, and temporarily store data input from an outside source; a...
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7603524 |
Method and apparatus for filtering snoop requests using multiple snoop caches
A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop...
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7603523 |
Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories...
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RE40921 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it...
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7590805 |
Monitor implementation in a multicore processor with inclusive LLC
A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always...
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7584331 |
Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout
In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first...
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7584330 |
Multi-processor data coherency
A method for maintaining coherent data in a multiprocessor system having a plurality of processors coupled to main memory, where each processor has an internal cache which is externally unreadable...
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7581068 |
Exclusive ownership snoop filter
A snoop filter maintains data coherency information for multiple caches in a multi-processor system. The Exclusive Ownership Snoop Filter only stores entries that are exclusively owned by a...
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7581064 |
Utilizing cache information to manage memory access and cache utilization
In a method of utilizing cache metadata to optimize memory access, cache metadata associated with a set of cache locations is inspected by software. The cache metadata is analyzed to determine...
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7577797 |
Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response
A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first...
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7577795 |
Disowning cache entries on aging out of the entry
Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the...
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7577794 |
Low latency coherency protocol for a multi-chip multiprocessor system
Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels...
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7568073 |
Mechanisms and methods of cache coherence in network-based multiprocessor systems with ring-based snoop response collection
A computer-implemented method for enforcing cache coherence includes multicasting a cache request for a memory address from a requesting node without an ordering restriction over a network,...
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7565558 |
Power saving method and system for a central processing unit disposed in a non-snooping sleep state when a peripheral device sends a bus master request
A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the...
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7555597 |
Direct cache access in multiple core processors
Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and...
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7546422 |
Method and apparatus for the synchronization of distributed caches
A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol...
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7546421 |
Interconnect transaction translation technique
A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined for a processor core within a...
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7543115 |
Two-hop source snoop based cache coherence protocol
A method for cache coherency in a network of a plurality of caching agents includes storing a plurality of miss requests, transmitting the miss requests into the network, sending a probe message on...
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7539823 |
Multiprocessing apparatus having reduced cache miss occurrences
A multiprocessing apparatus includes a cache control unit which monitors a local cache access signal, outputted from a processor, for notifying an occurrence of a cache miss, and notifies pseudo...
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7536515 |
Repeated conflict acknowledgements in a cache coherency protocol
In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict...
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7530066 |
Controlling snoop activities using task table in multiprocessor system
An embodiment of the present invention includes a task table to store a task entry corresponding to a first task associated with a first processor. A snoop controller controls snooping an access...
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7523268 |
Reducing number of rejected snoop requests by extending time to respond to snoop request
A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if...
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7523265 |
Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache
Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the...
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7512743 |
Using shared memory with an execute-in-place processor and a co-processor
The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be...
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7512741 |
Two-hop source snoop based messaging protocol
A messaging protocol that facilitates a distributed cache coherency conflict resolution in a multi-node system that resolves conflicts at a home node. The protocol may perform a method including...
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7502895 |
Techniques for reducing castouts in a snoop filter
Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality...
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7502893 |
System and method for reporting cache coherency state retained within a cache hierarchy of a processing node
A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to...
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7496713 |
Method and apparatus for maintaining cache coherency in a memory system with shared only cache memories
In data processing systems that use a snoopy based cache coherence protocol and which contain a read only cache memory with a bounded range of addresses, a cache line hit is detected by assuming...
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7484046 |
Reducing number of rejected snoop requests by extending time to respond to snoop request
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address,...
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7484044 |
Method and apparatus for joint cache coherency states in multi-interface caches
A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache...
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7478202 |
Using the message fabric to maintain cache coherency of local caches of global memory
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
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7472232 |
Method and related apparatus for internal data accessing of computer system
Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the...
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7472229 |
Bus controller initiated write-through mechanism
A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid,...
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7469275 |
System having interfaces, switch, and memory bridge for CC-NUMA operation
A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain...
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7469267 |
Method and system for host device event synchronization
A method and system for transferring control information between a host and network processor is provided. The system includes, a snooping module that is coupled to a snooping memory bus; a network...
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7464227 |
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an...
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7461213 |
Advanced processor system using request, data, snoop, and response rings
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and...
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7457924 |
Hierarchical directories for cache coherency in a multiprocessor system
Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory...
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7447845 |
Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality
A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array,...
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7437520 |
Adaptive snoop-and-forward mechanisms for multiprocessor systems
In a network-based cache-coherent multiprocessor system, when a node receives a cache request, the node can perform an intra-node cache snoop operation and forward the cache request to a subsequent...
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7434008 |
System and method for coherency filtering
Systems and methods for coherency filtering are disclosed. A system may comprise a coherency filter that provides information identifying a coherency domain for data in an associated address space...
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7418559 |
Address snoop method and multi-processor system
Address snoop methods and multi-processor systems to enable easy implementation of a large number of I/O blocks in the multi-processor system, independently of processor blocks, and to prevent the...
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7418558 |
Information processing system, system control apparatus, and system control method
A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control...
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7418557 |
Managing multiprocessor operations
In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first...
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