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9026742 System and method for processing potentially self-inconsistent memory transactions  
A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second...
9021211 Epoch-based recovery for coherent attached processor proxy  
A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP...
9015424 Write transaction management within a memory interconnect  
A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may...
9003130 Multi-core processing device with invalidation cache tags and methods  
A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated...
8990503 Monitoring multiple memory locations for targeted stores in a shared-memory multiprocessor  
A system and method for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second...
8990513 Accelerated recovery for snooped addresses in a coherent attached processor proxy  
A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality...
8959290 Methods and apparatus for reusing snoop responses and data phase results in a cache controller  
Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller,...
8949545 Memory interface device and methods thereof  
A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device,...
8949547 Coherency controller and method for data hazard handling for copending data access requests  
A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. Write requests are processed in a two part form, such that a first part is...
8938588 Ensuring forward progress of token-required cache operations in a shared cache  
Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is...
8930634 Speculative read in a cache coherent microprocessor  
A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent...
8930528 Method and system for partitioning directories  
A method of partitioning directory. Accesses, e.g., shared/exclusive, and/or waiting requests, e.g., shared/exclusive, to access one or more files with a directory are monitored, e.g.,...
8930638 Method and apparatus for supporting target-side security in a cache coherent system  
A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by...
8924653 Transactional cache memory system  
A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an...
8918591 Data processing system having selective invalidation of snoop requests and method therefor  
A data processing system includes a system interconnect, a processor coupled to the system interconnect, and a cache coherency manager (CCM) coupled to the system interconnect. The processor...
8918592 Extending a cache coherency snoop broadcast protocol with directory information  
In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information...
8909872 Computer system with coherent interconnection  
A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is...
8902915 Dataport and methods thereof  
A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such...
8898393 Optimized ring protocols and techniques  
Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a...
8886889 Methods and apparatus for reusing snoop responses and data phase results in a bus controller  
Methods and apparatus are provided for reusing snoop responses and data phase results in a bus controller. A bus controller receives an incoming bus transaction BTR1 corresponding to an incoming...
8886890 Adaptive configuration of cache  
A computer-implemented method for adaptively configuring a cache includes: implementing a cache adaptation agent in a system that has multiple applications, the system including a memory and a...
8868847 Multi-core processor snoop filtering  
Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit...
8856456 Systems, methods, and devices for cache block coherence  
Systems, methods, and devices for efficient cache coherence between memory-sharing devices are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block...
8856448 Methods and apparatus for low intrusion snoop invalidation  
Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a...
8856457 Information processing system and a system controller  
In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache...
8812793 Silent invalid state transition handling in an SMP environment  
Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state...
8806148 Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration  
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for...
8806147 System and method for creating ordering points  
A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data...
8799588 Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration  
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for...
8799587 Region coherence array for a mult-processor system having subregions and subregion prefetching  
A Region Coherence Array (RCA) having subregions and subregion prefetching for shared-memory multiprocessor systems having a single-level, or a multi-level interconnect hierarchy architecture.
8799589 Forward progress mechanism for stores in the presence of load contention in a system favoring loads  
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same...
8799586 Memory mirroring and migration at home agent  
Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a...
8799581 Cache coherence monitoring and feedback  
Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads...
8793442 Forward progress mechanism for stores in the presence of load contention in a system favoring loads  
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same...
8793327 Grid computing space  
A method and apparatus for using a tree-structured cluster as a library for a computing grid. In one embodiment, a request for computation is received at a cache node of the cluster. The...
8793439 Accelerating memory operations using virtualization information  
A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under...
8782348 Microprocessor cache line evict array  
An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy...
8782373 Seamless application access to hybrid main memory  
A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data...
8782349 System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message  
Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop...
8782347 Controllably exiting an unknown state of a cache coherency directory  
In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message...
8782434 System and method for validating program execution at run-time  
A pipelined processor comprising a cache memory system, fetching instructions for execution from a portion of said cache memory system, an instruction commencing processing before a digital...
8782435 System and method for validating program execution at run-time using control flow signatures  
A processor comprising: an instruction processing pipeline, configured to receive a sequence of instructions for execution, said sequence comprising at least one instruction including a flow...
8775775 Dynamic prefetch throttling for multi-controller systems  
A method for reading data from data storage is disclosed. A prefetch hint identifying a chunk of data a requesting node anticipates the requesting node will request that a controller retrieve from...
8775743 Resolving ownership deadlock in a distributed shared memory  
Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently...
8769211 Monitoring thread synchronization in a distributed cache  
Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread...
8756377 Area and power efficient data coherency maintenance  
An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for...
8751753 Coherence de-coupling buffer  
A coherence decoupling buffer. In accordance with a first embodiment of the present invention, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality...
8732412 Pruning obsolete messages in a distributed shared memory  
Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently...
8732410 Method and apparatus for accelerated shared data migration  
A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the...
8725958 Methods and systems for maintaining cache coherency in multi-processor systems  
The present invention provides a data processor capable of reducing power consumption at the time of execution of a spin wait loop for a spinlock. A CPU executes a weighted load instruction at the...