Matches 401 - 450 out of 640 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >
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6167500 Mechanism for queuing store data and method therefor  
A mechanism and method for a store data queue are implemented. Address translation operations for store instructions in a data processor are decoupled from data operations by initiating address...
6141735 Performing a memory access cycle in a multi-processor computer system  
In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of...
6141714 Method and apparatus for executing self-snooped unresolvable system bus operations  
A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it...
6141715 Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction  
A computer system avoids livelock conditions on a computer bus coupled to plural bus masters. In response to receiving a transaction request from a first bus master across the computer bus, a bus...
6138124 Field level replication method  
In a distributed computing system in which replicas of a document are separately stored and revised, the document containing data arranged in a number of fields, a method for replicating data...
6138218 Forward progress on retried snoop hits by altering the coherency state of a local cache  
When a device snooping the system bus of a multiprocessor system detects an operation requesting data which is resident within a local memory in a coherency state requiring the data to be sourced...
6138141 Server to client cache protocol for improved web performance  
On the Internet (106), rather than retrieving a frequently requested Web object from its originating server (105) in response to a request from a client terminal (101, 102), the object rather can...
6138217 Method and apparatus for cache coherency in an interconnecting network  
In a data processing system where a plurality of nodes, each having a plurality of processors and cache memories associated with each of the processors, are connected via a bus, tag information is...
6134634 Method and apparatus for preemptive cache write-back  
A microprocessor preemptively write-backs dirty entries of an internal cache. Each cache entry is checked once each predetermined time period to determine if the cache entry is dirty. If dirty, a...
6128706 Apparatus and method for a load bias--load with intent to semaphore  
Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias"...
6122691 Apparatus and method of layering cache and architectural specific functions to permit generic interface definition  
Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces...
6119204 Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization  
A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor...
6115796 Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions  
A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated...
6112231 Server to cache protocol for improved web performance  
On the Internet (106), rather than retrieving a frequently requested Web object from its originating server (105) in response to a request from a client terminal (101, 102), the object rather can...
6112283 Out-of-order snooping for multiprocessor computer systems  
In some embodiments, a computer system includes nodes connected through conductors. At least some of the nodes each include memory and processing circuitry to receive snoop requests in a node...
6105113 System and method for maintaining translation look-aside buffer (TLB) consistency  
A system and method for maintaining consistency between translational look-aside buffers (TLB) and page tables. A TLB has a TLB table for storing a list of virtual memory address-to-physical memory...
6101582 Dcbst with icbi mechanism  
Depending on a processor or instruction mode, a data cache block store (dcbst) or equivalent instruction is treated differently. A coherency maintenance mode for the instruction, in which the...
6098156 Method and system for rapid line ownership transfer for multiprocessor updates  
A method and system according to the present invention of accessing data in a multiprocessor system including a plurality of processors and a memory, wherein the memory includes a plurality of...
6088769 Multiprocessor cache coherence directed by combined local and global tables  
A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled...
6088773 Checkpoint acquisition accelerating apparatus  
A novel checkpoint acquisition accelerating apparatus is disclosed. When data are updated on a cache memory, a before-image acquiring section acquires the update address and the previous data and...
6085330 Control circuit for switching a processor between multiple low power states to allow cache snoops  
Power consumption is conserved in a computer system by, instead of forcing a processor to change from the stop clock state to a fully operational state, allowing the processor to transition from...
6081876 Memory error containment in network cache environment via restricted access  
A computer memory management system that allocates each node's network cache into protected and unprotected regions. Nodes are previously configured into error containment cluster of nodes (ECCNs)....
6076147 Non-inclusive cache system using pipelined snoop bus  
A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data...
6076139 Multimedia computer architecture with multi-channel concurrent memory access  
A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to...
6076120 System for compositing a plurality of pages said pages being classified into three parts each part to be composed in a different data format  
Data formats (page description data, intermediate data and raster data) for compositing respective ones of first to fifth pages with each other are previously determined. An interpreter and a...
6073217 Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor  
A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction...
6073212 Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags  
An apparatus and method for optimizing a non-inclusive hierarchical cache memory system that includes a first and second cache for storing information. The first and second cache are arranged in an...
6073199 History-based bus arbitration with hidden re-arbitration during wait cycles  
An arbiter uses a history based bus arbitration scheme to more fairly allocate a shared resource among multiple devices. The arbiter uses a history queue to dynamically update the priorities of the...
6070233 Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache  
A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status...
6065098 Method for maintaining multi-level cache coherency in a processor with non-inclusive caches and processor implementing the same  
The processor includes at least a lower and a higher level non-inclusive cache, and a system bus controller. The system bus controller snoops commands on the system bus, and supplies the snooped...
6061765 Independent victim data buffer and probe buffer release control utilzing control flag  
In accordance with the present invention, a method and apparatus is provided for storing victim data evicted from a cache and for satisfying pending requests or probe messages that target victim...
6061755 Method of layering cache and architectural specific functions to promote operation symmetry  
Cache and architectural functions within a cache controller are layered so that architectural operations may be symmetrically treated regardless of whether initiated by a local processor or by a...
6061762 Apparatus and method for separately layering cache and architectural specific functions in different operational controllers  
Cache and architectural specific functions are layered within a controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be...
6061766 Non-inclusive cache method using pipelined snoop bus  
A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data...
6055608 Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system  
A method and system for speculatively sourcing data from a cache memory within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present...
6052762 Method and apparatus for reducing system snoop latency  
In multi-processor systems which have separated the system bus from the I/O bus, a Shadow Directory is introduced into the memory controller for reducing bottlenecks that occur from the processors...
6049849 Imprecise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests  
A method and system for managing a cache including a plurality of entries are described. According to the method, first and second cache operation requests are received. In response to receipt of...
6049851 Method and apparatus for checking cache coherency in a computer architecture  
A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a...
6047355 Symmetric multiprocessing system with unified environment and distributed system functions  
A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution...
6038644 Multiprocessor system with partial broadcast capability of a cache coherent processing request  
Information indicative of whether each processor unit caches data which belongs to each of the plural areas of the main memory larger than a cache line is stored in the multicast table. The...
6032231 Multiprocessor with split transaction bus architecture providing cache tag and address compare for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag  
A method and system for arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a...
6029204 Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries  
A method of synchronizing an initiating processing unit in a multi-processor computer system with other processing units in the system, by assigning a unique tag for each processing unit, and...
6026470 Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels  
A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function,...
6021474 Apparatus and method of snooping processors and look-aside caches  
The present invention provides a method and apparatus for providing memory coherency among an L1 and an L2 cache memory devices and a main memory device. In an embodiment of the invention, a memory...
6021468 Cache coherency protocol with efficient write-through aliasing  
A method of maintaining cache coherency in a multi-processor computer system, which avoids unnecessary writing of values to lower level caches in response to write-through store operations. When a...
6018792 Apparatus for performing a low latency memory read with concurrent snoop  
A computer system has a system memory, cache memory, system controller that process memory transactions. The system controller transmits a memory request to the system memory without waiting for...
6018791 Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states  
A multi-processor computer system with clustered processing units uses a cache coherency protocol having a "recent" coherency state to indicate that a particular cache block containing a valid copy...
6016551 Method and apparatus for masking and unmasking a clock signal in an integrated circuit  
A microprocessor having a cache memory unit, an execution unit, and clock masking circuitry is described. Both units are responsive to a clock signal that can be masked by the clock masking...
6014721 Method and system for transferring data between buses having differing ordering policies  
A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering...
6006312 Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses  
A separate cacheable-in-virtual-cache attribute bit (CV) is maintained for each page of memory in the translation table maintained by the operating system. The CV bit indicates whether the memory...
Matches 401 - 450 out of 640 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >