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6801984 |
Imprecise snooping based invalidation mechanism
A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided...
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6785774 |
High performance symmetric multiprocessing systems via super-coherent data mechanisms
A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that,...
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6785773 |
Verification of global coherence in a multi-node NUMA system
A system and method for verifying cache coherency in a multi-node, NUMA system includes a transaction modification unit configured to receive event traces generated by a simulation tool. The...
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6785775 |
Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues
A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies...
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6785769 |
Multi-version data caching
A system and method for caching multiple versions of a data item (e.g., web page, portion of a web page, data table, data object) and determining which of the multiple versions is most responsive...
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6785779 |
Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architecture
A method of classification of transaction address conflicts in a computer system for ensuring efficient ordering in a two-level snoopy cache architecture. The disclosure provides a method of...
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6779086 |
Symmetric multiprocessor systems with an independent super-coherent cache directory
A multiprocessor data processing system comprising, in addition to a first and second processor having an respective first and second cache and a main cache directory affiliated with the first...
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6775749 |
System and method for performing a speculative cache fill
A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in...
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6775748 |
Methods and apparatus for transferring cache block ownership
Methods and apparatus for transferring cache block ownership from a first cache to a second cache without performing a writeback to a main memory are disclosed. Prior to the ownership transfer, the...
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6763434 |
Data processing system and method for resolving a conflict between requests to modify a shared cache line
Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect...
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6763433 |
High performance cache intervention mechanism for symmetric multiprocessor systems
Upon snooping an operation in which an intervention is permitted or required, an intervening cache may elect to source only that portion of a requested cache line which is actually required, rather...
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6763436 |
Redundant data storage and data recovery system
A data replication system is disclosed in which replication functionalities between a host computer, an interconnecting computer network, and a plurality of storage devices are separated into host...
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6763435 |
Super-coherent multiprocessor system bus protocols
A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system...
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6760817 |
Method and system for prefetching utilizing memory initiated prefetch write operations
A computer system includes a processing unit, a system memory, and a memory controller coupled to the processing unit and the system memory. According to the present invention, the memory...
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6760819 |
Symmetric multiprocessor coherence mechanism
A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced...
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6757790 |
Distributed, scalable data storage facility with cache memory
The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the...
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6754782 |
Decentralized global coherency management in a multi-node computer system
A non-uniform memory access (NUMA) computer system includes a first node and a second node coupled by a node interconnect. The second node includes a local interconnect, a node controller coupled...
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6748463 |
Information processor with snoop suppressing function, memory controller, and direct memory access processing method
An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In...
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6748497 |
Systems and methods for buffering memory transactions
An apparatus and method for memory transaction buffering are implemented. Read and write buffer units are provided. The read buffer unit is configured for storing at least one data value read from...
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6745298 |
Internal processor buffering for implicit writebacks
A method and apparatus for processing data is described. A request such as a multiprocessor snoop request for data is received from a bus. A determination is made as to whether a cache contains the...
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6735675 |
Method and apparatus for altering data length to zero to maintain cache coherency
Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the...
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6728258 |
Multi-processor system and its network
In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the...
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6728842 |
Cache updating in multiprocessor systems
Embodiments are provided in which cache update is implemented by using a counter table having a plurality of entries to keep track of different modified cache lines of a cache of a processor. If a...
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6728841 |
Conserving system memory bandwidth during a memory read operation in a multiprocessing computer system
A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a...
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6725344 |
Sram with tag and data arrays for private external microprocessor bus
The present invention includes a microprocessor having a system bus for exchanging data with a computer system, and a private bus for exchanging data with a cache memory system. Since the processor...
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6721856 |
Enhanced cache management mechanism via an intelligent system bus monitor
In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access, snoop operation, and system controller hint information for...
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6718839 |
Method and apparatus for facilitating speculative loads in a multiprocessor system
One embodiment of the present invention provides a system that facilitates speculative load operations in a multiprocessor system. The system operates by maintaining a record of speculative load...
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6721855 |
Using an L2 directory to facilitate speculative loads in a multiprocessor system
One embodiment of the present invention provides a system that facilitates speculative load operations in a multiprocessor system. This system operates by maintaining a record at an L2 cache of...
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6718400 |
Data accessing system with an access request pipeline and access method thereof
A PCI data accessing system with a read request pipeline and an application method thereof are provided. The PCI data accessing system has a PCI master device, a memory module, and a PCI control...
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6711653 |
Flexible mechanism for enforcing coherency among caching structures
The present invention provides a computer system that is capable of operating in a first or second cache coherency mode according to the operating environment in which the computer system is booted...
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6704845 |
Snoop filter line replacement for reduction of back invalidates in multi-node architectures
A snoop filter in a multi-processor system maintains a plurality of entries, each representing a cache line that may be owned by one or more nodes. When replacement of one of the entries is...
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6704842 |
Multi-processor system with proactive speculative data transfer
A network of memory and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor system. The nodes contain multiple processors operatively connected via...
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6704841 |
Method and apparatus for facilitating speculative stores in a multiprocessor system
One embodiment of the present invention provides a system for facilitating speculative store operations in a multiprocessor system. This system operates by maintaining a record of speculative store...
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6704844 |
Dynamic hardware and software performance optimizations for super-coherent SMP systems
A method for increasing performance optimization in a multiprocessor data processing system. A number of predetermined thresholds are provided within a system controller logic and utilized to...
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6704843 |
Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange
System bus snoopers within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the dynamic application sequence behavior...
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6687795 |
Data processing system and method of communication that reduce latency of write transactions subject to retry
A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry...
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6684398 |
Monitor entry and exit for a speculative thread during space and time dimensional execution
One embodiment of the present invention provides a system that facilitates entering and exiting a critical section of code for a speculative thread. The system supports a head thread that executes...
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6681292 |
Distributed read and write caching implementation for optimized input/output applications
A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory...
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6678795 |
Method and apparatus for memory prefetching based on intra-page usage history
There is provided a method for fetching at least one of instructions and operand data from a second memory into a first memory of a computer system having at least one processor. The method...
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6668309 |
Snoop blocking for cache coherency
In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If...
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6658545 |
Passing internal bus data external to a completed system
An apparatus and technique to allow internal bus activity of a system on a chip to be monitored external to the integrated circuit, but without requiring additional external pins. A snooping pass...
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6651115 |
DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces
In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each...
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6640288 |
Read exclusive for fast, simple invalidate
An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates. Additionally, the agent is configured to...
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6636925 |
Bus interface circuit preparation apparatus and recording medium
An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware...
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6636939 |
Method and apparatus for processor bypass path to system memory
A memory interface unit is described having a first interface to receive a first request from a processor where the first request has an attribute. The memory interface unit also has a second...
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6636906 |
Apparatus and method for ensuring forward progress in coherent I/O systems
A snapshot mechanism that includes an apparatus and method for tracking DMA read requests for cacheable data that can be altered before the data is returned to a requesting I/O device is herein...
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6631450 |
Symmetric multiprocessor address bus protocol with intra-cache line access information
System bus masters within a multiprocessor system in which dynamic application sequence behavior information is maintained within cache directories append the historical access information for the...
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6631448 |
Cache coherence unit for interconnecting multiprocessor nodes having pipelined snoopy protocol
The present invention consists of a cache coherence protocol within a cache coherence unit for use in a data processing system. The data processing system is comprised of multiple nodes, each node...
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6622214 |
System and method for maintaining memory coherency in a computer system having multiple system buses
A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while...
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6622216 |
Bus snooping for cache coherency for a bus without built-in bus snooping capabilities
A computer system incorporates bus snooping with a bus that does not enable bus snooping, such as the Advanced High-Performance Bus (AHB), to maintain cache coherency between caching devices and...
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