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6993633 Computer system utilizing speculative read requests to cache memory  
A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data...
6993632 Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent  
A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response...
6988170 Scalable architecture based on single-chip multiprocessing  
A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory...
6988166 Method for snooping raid 1 read transactions by a storage device  
To implement a RAID 1 transaction, an initiator sends a single command, i.e., either a single read command, or a single write command, over a common I/O bus to a primary target device. A mirror...
6986005 Low latency lock for multiprocessor computer system  
A multinodal multiprocessor computer system and method is provided in which a first processor can acquire exclusive access to a first memory location in a shared memory, and at the same time a...
6986002 Adaptive shared data interventions in coupled broadcast engines  
The present invention provides for a bus system having a local bus ring coupled to a remote bus ring. A processing unit is coupled to the local bus node and is employable to request data. A cache...
6985972 Dynamic cache coherency snooper presence with variable snoop latency  
A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus...
6983348 Methods and apparatus for cache intervention  
Methods and Apparatus for cache-to-cache transfers upon snooping a cache interconnect to detect a memory read request associated with a cache memory block cached in a first cache and a second...
6983347 Dynamically managing saved processor soft states  
A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process...
6981106 System and method for accelerating ownership within a directory-based memory system  
The current invention provides a system and method for managing data stored within a main storage device such as a main memory. In one embodiment, multiple requesters are coupled to the main...
6976132 Reducing latency of a snoop tenure  
A method and system for reducing latency of a snoop tenure. A bus macro may receive a snoopable transfer request. The bus macro may determine which snoop controllers in a system will participate in...
6976129 Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture  
A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment,...
6976131 Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system  
A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having...
6973546 Method, system, and program for maintaining data in distributed caches  
Provided are a method, system, and program for maintaining data in distributed caches. A copy of an object is maintained in at least one cache, wherein multiple caches may have different versions...
6970982 Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions  
A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of...
6968431 Method and apparatus for livelock prevention in a multiprocessor system  
In a multiprocessor system using snooping protocols, system command conflicts are prevented by comparing processor commands with prior snoops within a specified time defined window. A determination...
6959364 Partially inclusive snoop filter  
In some embodiments, the invention includes a snoop filter, wherein entries in the snoop filter are allocated in response to initial accesses of local cache lines by a remote node, but entries in...
6950909 System and method for reducing contention in a multi-sectored cache  
A cache access mechanism/system for reducing contention in a multi-sectored cache via serialization of overlapping write accesses to different blocks of a cache line to enable accurate cache...
6950908 Speculative cache memory control method and multi-processor system  
The processors # 0 to # 3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor # 1 that executes a thread updates the self-cache memory # 1, if...
6944721 Asynchronous non-blocking snoop invalidation  
A method and system for avoiding live locks caused by repeated retry responses sent from a first cache memory that is in the process of manipulating a cache line that a second cache memory is...
6931495 Processor and method of arithmetic processing thereof  
A processor system, comprising: a processor having a function to write back data stored in a cache memory to an external memory in units of a cache line formed of a plurality of words; a small unit...
6928517 Method for avoiding delays during snoop requests  
A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP...
6925537 Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants  
A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and...
6922756 Forward state for use in cache coherency in a multiprocessor system  
Described herein is a cache coherency protocol having five states: Modified, Exclusive, Shared, Invalid and Forward (MESIF). The MESIF cache coherency protocol includes a Forward (F) state that...
6922755 Directory tree multinode computer system  
A multinode, multiprocessor computer system with distributed shared memory has reduced hardware and improved performance by providing a directory free environment. Without a directory, nodes do not...
6907502 Method for moving snoop pushes to the front of a request queue  
A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request...
6898675 Data received before coherency window for a snoopy bus  
Where a null response can be expected from devices snooping a load operation, data may be used by a requesting processor prior to the coherency response window. A null snoop response may be...
6898676 Computer system supporting both dirty-shared and non-dirty-shared data processing entities  
A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer...
6895477 Ring-based memory requests in a shared memory multi-processor  
A system includes a plurality of processing clusters and a snoop controller adapted to service memory requests. The snoop controller and each processing cluster are coupled to a snoop ring. A first...
6892282 Ring based multi-processing system  
A multi-processor unit includes a set of processing clusters. Each processing cluster is coupled to a data ring and a snoop ring. The unit also includes a snoop controller adapted to process memory...
6883070 Bandwidth-adaptive, hybrid, cache-coherence protocol  
A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence...
6880031 Snoop phase in a highly pipelined bus architecture  
A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a...
6877029 Method and apparatus for managing node controllers using partitions in a computer system  
A partitioned computer system ( 32 ) includes a plurality of node controllers ( 12 ) connected by a network ( 14 ) and partitioned into a plurality of partitioned groups ( 40 ). A requesting node...
6871268 Methods and systems for distributed caching in presence of updates and in accordance with holding times  
Techniques for improved cache management including cache replacement are provided. In one aspect, a distributed caching technique of the invention comprises the use of a central cache and one or...
6871267 Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency  
A multi-processor system includes a system bus communicating between processors, and a bus arbiter. Responsive to a cache line invalidation command, a processor cache conditionally casts back the...
6865649 Method and apparatus for pre-fetching data during program execution  
A system and method for pre-fetching data. A computer program comprising multiple basic blocks is submitted to a processor for execution. Tables or other data structures are associated with some or...
6865595 Methods and apparatus for speculative probing of a remote cluster  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for...
6862665 Method, system, and apparatus for space efficient cache coherency  
A schematic, system, and flowchart to facilitate storage of directory information for a cache coherency protocol. The protocol allows for at least a single bit of directory information overwriting...
6859864 Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line  
A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read...
6857048 Pseudo least-recently-used (PLRU) replacement method for a multi-node snoop filter  
A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches is provided with a Pseudo Least-Recently-Used (PLRU)...
6848032 Pipelining cache-coherence operations in a shared-memory multiprocessing system  
One embodiment of the present invention provides a system that facilitates pipelining cache coherence operations in a shared memory multiprocessor system. During operation, the system receives a...
6842827 Cache coherency arrangement to enhance inbound bandwidth  
A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed....
6836829 Peripheral device interface chip cache and data synchronization method  
A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The...
6836826 Multilevel cache system and method having a merged tag array to store tags for multiple data arrays  
A multilevel cache system and method. A first data array and a second data array are coupled to a merged tag array. The merged tag array stores tags for both the first data array and second data...
6829665 Next snoop predictor in a host controller  
A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which...
6826656 Reducing power in a snooping cache based multiprocessor environment  
A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache...
6823409 Coherency control module for maintaining cache coherency in a multi-processor-bus system  
A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.
6810467 Method and apparatus for centralized snoop filtering  
An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and...
6807608 Multiprocessor environment supporting variable-sized coherency transactions  
A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request)...
6801984 Imprecise snooping based invalidation mechanism  
A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided...
Matches 151 - 200 out of 638 < 1 2 3 4 5 6 7 8 9 10 11 12 13 >