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7237070 |
Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source
At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache...
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7234029 |
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are...
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7225300 |
Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system
Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two...
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7222220 |
Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices
A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the...
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7210007 |
Method of verifying a system in which a plurality of master devices share a storage device
In logical verification of a system in which a plurality of master devices share a storage region, a scoreboard common to all master devices is provided. When starting verification, an initial...
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7194586 |
Method and apparatus for implementing cache state as history of read/write shared data
A method and apparatus are provided for implementing a cache state as history of read/write shared data for a cache in a shared memory multiple processor computer system. An invalid temporary state...
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7177987 |
System and method for responses between different cache coherency protocols
Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency...
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7174430 |
Bandwidth reduction technique using cache-to-cache transfer prediction in a snooping-based cache-coherent cluster of multiprocessing nodes
A multiprocessing node in a snooping-based cache-coherent cluster of processing nodes maintains a cache-to-cache transfer prediction directory of addresses of data last transferred by...
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7171520 |
Cache flush system and method thereof
The present invention relates to a cache flush system and the method for a cache flush performed in cache memory against at least one corresponding prescribed event in a multi-processor system....
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7159077 |
Direct processor cache access within a system having a coherent multi-processor protocol
A computer system has a plurality of processors in a multiprocessor system with each processor associated with a cache memory. The cache traffic is monitored by the respective processors to...
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7159079 |
Multiprocessor system
A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 ...
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7149852 |
System and method for blocking data responses
Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that...
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7149855 |
Network attached memory and implementation thereof
A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other...
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7146468 |
Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache
A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query...
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7143246 |
Method for supporting improved burst transfers on a coherent bus
In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A...
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7143245 |
System and method for read migratory optimization in a cache coherency protocol
A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to...
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7136969 |
Using the message fabric to maintain cache coherency of local caches of global memory
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
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7130969 |
Hierarchical directories for cache coherency in a multiprocessor system
Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory...
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7127562 |
Ensuring orderly forward progress in granting snoop castout requests
A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request...
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7120755 |
Transfer of cache lines on-chip between processing cores in a multi-core system
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific...
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7117311 |
Hot plug cache coherent interface method and apparatus
A computing device maintains coherency while supporting addition and removal of memory caching agents without rebooting the computing device.
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7117312 |
Mechanism and method employing a plurality of hash functions for cache snoop filtering
A mechanism for filtering snoop requests to a cache memory includes, in one embodiment, a first storage that may store a first set of corresponding snoop filter indications. The mechanism also...
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7114038 |
Method and apparatus for communicating between integrated circuits in a low power mode
For one embodiment, a computer system includes both high power and low power buses coupling a processor to a controller. When the processor is in a high power mode, its cache is snooped by the...
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7107408 |
Methods and apparatus for speculative probing with early completion and early request
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller...
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7107409 |
Methods and apparatus for speculative probing at a request cluster
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A cache coherence controller...
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7103726 |
Methods and apparatus for managing probe requests
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the...
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7103725 |
Methods and apparatus for speculative probing with early completion and delayed request
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller...
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7103636 |
Methods and apparatus for speculative probing of a remote cluster
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for...
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7093079 |
Snoop filter bypass
Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may...
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7089361 |
Dynamic allocation of shared cache directory for optimizing performance
Methods, apparatus, and program product are disclosed for use in a computer system to provide for dynamic allocation of a directory memory in a node memory controller in which one or more coherent...
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7089376 |
Reducing snoop response time for snoopers without copies of requested data via snoop filtering
In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering...
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7085885 |
Apparatus and method for early cache miss detection
A cache memory that notifies other functional blocks in the microprocessor that a miss has occurred potentially N clocks sooner than the conventional method, where N is the number of stages in the...
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7085898 |
Coherency management for a “switchless” distributed shared memory computer system
An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O...
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7082501 |
Remote node accessing local memory by using distributed shared memory
A DSM system includes a local node, a first remote node, and a second remote nodes. The data access method for a remote node to access a local node in the DSM system includes the steps of directly...
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7080209 |
Method and apparatus for processing a load-lock instruction using a relaxed lock protocol
A processing core using a lock scoreboard mechanism is provided. The lock scoreboard is adapted to manage a load-lock instruction. The load-lock scoreboard includes a plurality of scoreboard...
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7080198 |
Method for snooping RAID 1 write transactions by a storage device
To implement a RAID 1 transaction, an initiator sends a single command, i.e., either a single read command, or a single write command, over a common I/O bus to a primary target device. A mirror...
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7073043 |
Multiprocessor system supporting multiple outstanding TLBI operations per partition
Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete...
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7073030 |
Method and apparatus providing non level one information caching using prefetch to increase a hit ratio
A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1...
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7069391 |
Method for improved first level cache coherency
A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from invalidating level one cache...
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7062613 |
Methods and apparatus for cache intervention
Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a...
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7062612 |
Updating remote locked cache
A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is...
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7043612 |
Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data
An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a...
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7039768 |
Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions
A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the...
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7032078 |
Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols
A multiprocessor computer system to selectively transmit address transactions using a broadcast mode or a point-to-point mode. Either a directory-based coherency protocol or a broadcast snooping...
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7032079 |
System and method for accelerating read requests within a multiprocessor system
A system and method for managing memory data within a data processing system is disclosed. A main memory is provided to store data signals. When the main memory receives a request to read data...
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7024521 |
Managing sparse directory evictions in multiprocessor systems via memory locking
Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache...
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7020752 |
Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory unit
In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at...
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7017031 |
Method, apparatus and system for managing released promotion bits
A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion...
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7003633 |
Methods and apparatus for managing probe requests
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the...
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6993633 |
Computer system utilizing speculative read requests to cache memory
A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data...
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