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7418559 |
Address snoop method and multi-processor system
Address snoop methods and multi-processor systems to enable easy implementation of a large number of I/O blocks in the multi-processor system, independently of processor blocks, and to prevent the...
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7418556 |
Accessing memory and processor caches of nodes in multi-node configurations
A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a...
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7409500 |
Systems and methods for employing speculative fills
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data...
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7409503 |
Register file systems and methods for employing speculative fills
Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that...
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7409481 |
Data processing system, method and interconnect fabric supporting destination data tagging
A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes...
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7406566 |
Ring interconnect with multiple coherence networks
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments...
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7406565 |
Multi-processor systems and methods for backup for non-coherent speculative fills
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with...
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7406571 |
Memory system and method for controlling the same, and method for maintaining data coherency
A memory system including a bus 10, 11 , a memory 17 , a memory controller 16 , a first device 13 having a cache, and a second device 15 , all connected to the bus, wherein the memory...
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7404047 |
Method and apparatus to improve multi-CPU system performance for accesses to memory
Methods and apparatuses for improving processor performance in a multi-processor system by optimizing accesses to memory. Processors can track the state of a memory such that the memory can be...
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7404044 |
System and method for data transfer between multiple processors
A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In...
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7404046 |
Cache memory, processing unit, data processing system and method for filtering snooped operations
A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache...
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7401209 |
Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction
A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load...
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7398361 |
Combined buffer for snoop, store merging, load miss, and writeback operations
In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests...
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7395380 |
Selective snooping by snoop masters to locate updated data
A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less...
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7395381 |
Method and an apparatus to reduce network utilization in a multiprocessor system
A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor...
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7395376 |
Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of shared memory blocks
A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast local requests to reduce the latency to access data from remote nodes in an SMP...
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7395379 |
Methods and apparatus for responding to a request cluster
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors...
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7395374 |
System and method for conflict responses in a cache coherency protocol with ordering point migration
Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first...
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7395375 |
Prefetch miss indicator for cache coherence directory misses on external caches
A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache...
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7392351 |
Method and apparatus for filtering snoop requests using stream registers
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated...
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7392350 |
Method to operate cache-inhibited memory mapped commands to access registers
In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the...
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7392346 |
Memory updater using a control array to defer memory operations
A memory having multiple locations for data storage is updated by performing the following method. The memory locations are grouped into commonly accessible groups of one or more data locations....
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7386684 |
Method and apparatus for detecting a cache wrap condition
A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have...
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7383398 |
Preselecting E/M line replacement technique for a snoop filter
A snoop filter maintains data coherency information for multiple caches in a multi-processor system. When a new request for a memory line arrives, an entry of the snoop filter is selected for...
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7383336 |
Distributed shared resource management
A method for processing data in a computer system using two main concepts for addressing this situation, from which numerous other implementations is achieved using a first and second main concept....
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7383409 |
Cache systems and methods for employing speculative fills
One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in...
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7380071 |
Snoop filtering system in a multiprocessor system
A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The...
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7376794 |
Coherent signal in a multi-processor system
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source...
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7373466 |
Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a...
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7373462 |
Snoop filter for filtering snoop requests
A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories...
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7370155 |
Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response
A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor...
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7360031 |
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface...
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7356652 |
System and method for selectively storing bus information associated with memory coherency operations
A manner for judiciously snooping or otherwise monitoring bus operations associated with maintaining cache or other memory coherency in a computing system. A bus snoop information storage mode is...
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7353341 |
System and method for canceling write back operation during simultaneous snoop push or snoop kill operation in write back caches
A cache write back operation, write back modified data to memory from cache data array to fix inconsistency between them can be cancelled by the results of a comparison of the progress between a...
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7340565 |
Source request arbitration
Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in...
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7337279 |
Methods and apparatus for sending targeted probes
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the...
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7330939 |
Determining an amount of data read from a storage medium
Data is read in response to a request for a predetermined amount of data. The amount of data that has been read is determined prior to completing reading the predetermined amount of data. The...
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7330925 |
Transaction flow control mechanism for a bus bridge
A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow...
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7325102 |
Mechanism and method for cache snoop filtering
A mechanism for filtering snoop requests to a cache memory includes, in one embodiment, a storage including a plurality of entries configured to store corresponding snoop filter indications. The...
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7320054 |
Multiprocessor system having a shared memory
Disclosed is a multiprocessor system in which even if contention occurs when a common memory is accessed from each of a plurality of processors, the number of times the common memory is accessed is...
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7318126 |
Asynchronous symmetric multiprocessing
An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for...
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7315919 |
Bandwidth reduction technique in a snooping-based cache-coherent cluster of multiprocessing nodes
A cluster of multiprocessing nodes uses snooping-based cache-coherence to maintain consistency among the cache memories of the multiprocessing nodes. One or more of the multiprocessing nodes each...
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7305524 |
Snoop filter directory mechanism in coherency shared memory system
Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout...
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7305525 |
Memory system for network broadcasting applications and method for operating the same
A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a...
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7290115 |
System and method for filtering write operations to a storage medium containing an operating system image
A write filter is used to handle write operations by an operating system of a computing device that has a main storage medium in which the operating system image is stored. The write filter is...
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7284097 |
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going...
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7275125 |
Pipeline bit handling circuit and method for a bus bridge
A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a...
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7275124 |
Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability
A bus bridge for coupling between a first bus and a second bus includes: a number of data buffers for a particular request type; a counter for monitoring a number of requests of the particular type...
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7263586 |
Cache coherency for multiple independent cache of a domain
Distinguishing between snoops initiated internally with respect to a processing unit and snoops initiated externally with respect to a processing unit allows maintenance of cache coherency for a...
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7238218 |
Memory prefetch method and system
Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are...
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