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5829037 Multiprocessor system having a large number of processor system components connected to a plurality of serial high-speed-buses  
A multiprocessor system has a plurality of serial system buses arranged in parallel to which is connected a large number of system components (PSK1, PSK, SSK). The system components (PSK1, PSKm,...
5822765 System and method for resolving contention arising from execution of cache coherency operations in a multiple cache computer system  
A data processing system and method having a number of cache controllers coupled to a bus. A cache controller uses a buffer operably coupled to the bus for loading information from the bus. A...
5822767 Method and apparartus for sharing a signal line between agents  
Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and...
5819105 System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device  
A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are...
5815675 Method and apparatus for direct access to main memory by an I/O bus  
A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place...
5813034 Method and circuitry for modifying data words in a multi-level distributed data processing system  
A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the...
5813035 Microprocessor employing a technique for restoration of an aborted cycle following a snoop writeback operation  
A microprocessor is provided with an output pad logic circuit for each of its output lines. Each output pad logic circuit advantageously includes first and second latch circuits each configured to...
5812815 Address tenure control for cache management wherein bus master addresses are internally latched in a cache controller  
Systems and methods which provide a minimized address tenure to create more efficient memory transactions where the address is not needed for longer than the initial clock cycle in which it is used...
5813022 Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus  
A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant...
5809537 Method and system for simultaneous processing of snoop and cache operations  
A method and system for simultaneous retrieval of snoop address information in conjunction with the retrieval/storing of a cache line load/store operation. The method and system are implemented in...
5809532 Data processor with cache and method of operation  
A data processor (10) has a data cache (16) that supports snooping operations and conserves power. A freeze logic unit (46) enables the data cache when the data cache performs a load/store...
5809280 Adaptive ahead FIFO with LRU replacement  
A plurality of read-ahead FIFOs, each with an LRU replacement policy, is provided for enhancing buffer performance. The FIFO contains a plurality of adaptive buffer replacement counters to monitor...
5809533 Dual bus system with multiple processors having data coherency maintenance  
A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through...
5806086 Multiprocessor memory controlling system associating a write history bit (WHB) with one or more memory locations in controlling and reducing invalidation cycles over the system bus  
A memory controller system for use with a plurality of processor nodes capable of reducing the number of invalidate cycles on a shared system bus in cache coherent non-uniform memory architecture...
5802576 Speculative cache snoop during DMA line update  
A method and apparatus for facilitating the streaming of data over a system bus between a memory and a DMA device. This is accomplished by doing a speculative cache look-up, or snoop, on a next...
5802577 Multi-processing cache coherency protocol on a local bus  
A computer system maintaining cache coherency among a plurality of caching devices coupled across a local bus includes a bus master, a memory, and a plurality of cache complexes, all coupled to the...
5802574 Method and apparatus for quickly modifying cache state  
The state of cached data may be modified without performing a tag comparison. Each cache line includes at least one attribute bit and at least one state bit. A processor issues an instruction...
5802559 Mechanism for writing back selected doublewords of cached dirty data in an integrated processor  
An integrated processor is provided that includes a cache controller which keeps track of a physical address in the system memory which corresponds to each entry within the cache memory. The...
5802567 Mechanism for managing offset and aliasing conditions within a content-addressable memory-based cache memory  
A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory...
5802562 Information processing system and including a supplemental memory and method of operation  
An information processing system and method of operation are provided. In response to a first instruction, a supplemental memory stores first information from a system memory. In response to a...
5796980 Reducing cache snooping overhead in a multilevel cache system with inclusion field in shared cache indicating state of data in lower level caches  
A memory system for reducing cache snooping overhead for a two level cache system with multiple bus masters, has a level 2 cache connected to a main memory and a level 1 cache connected to a bus...
5796977 Highly pipelined bus architecture  
A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents...
5797026 Method and apparatus for self-snooping a bus during a boundary transaction  
A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The...
5787465 Destination indexed miss status holding registers  
A hierarchical memory arrangement for use with a processor includes a cache, addressable by source addresses, and a set of processor registers, addressable by destination addresses. For each...
5787441 Method of replicating data at a field level  
In a distributed computing system in which replicas of a document are separately stored and revised, the document containing data arranged in a number of fields, a method for replicating data...
5781757 Adaptive scalable cache coherence network for a multiprocessor data processing system  
A cache coherence network for transferring coherence messages between processor caches in a multiprocessor data processing system is provided. The network includes a plurality of processor caches...
5778434 System and method for processing multiple requests and out of order returns  
A system and method for processing a sequence of requests for data by one or more central processing units (CPUs) after cache misses. Each CPU request includes a CPU-ID tag identifying the CPU...
5778437 Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory  
An optimization scheme for a directory-based cache coherence protocol for multistage interconnection network-based multiprocessors improves system performance by reducing network latency. The...
5774700 Method and apparatus for determining the timing of snoop windows in a pipelined bus  
A method and apparatus for determining the timing of snoop windows in a pipelined bus includes a snoop timer, a snoop counter, and snoop resolution logic. The snoop timer indicates the number of...
5768558 Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle  
A computer system includes a microprocessor having an internal cache memory and control unit that performs write-back operations to external memory responsive to an external signal indicating that...
5765208 Method of speculatively executing store instructions prior to performing snoop operations  
A data processor (10) has a load/store unit (28) that executes store-to-shared-data instructions before it exclusively owns the data designated by the instruction. Later, a bus interface unit (12)...
5764932 Method and apparatus for implementing a dual processing protocol between processors  
To improve computer performance, a second processor can be added to a computer system. However, when a second processor is added to a computer system, a dual processing protocol is required to...
5761725 Cache-based computer system employing a peripheral bus interface unit with cache write-back suppression and processor-peripheral communication suppression for data coherency  
A peripheral bus interface unit is provided that includes a data storage unit for temporarily storing data written from a peripheral unit, and a control unit that executes a write cycle on a system...
5754816 Data storage apparatus and method with two stage reading  
A data memory is described in which data words comprising access control bits and further bits are stored at each memory location 34. When a particular memory location is addressed, then the access...
5752265 Memory accessing in a multi-processor system using snooping  
In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of...
5751995 Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively  
In a computer system having a plurality of processors, an apparatus and method for maintaining processor ordering associated with read and write operations of these processors. When data from a...
5751986 Computer system with self-consistent ordering mechanism  
A computer system including a processor having a inherently weakly-ordered memory model comprising a mechanism for emulating strong-ordering to produce self-consistent ordering on a system-wide...
5749087 Method and apparatus for maintaining n-way associative directories utilizing a content addressable memory  
A method and apparatus are provided for maintaining a N-way associative directory utilizing a content addressable memory (CAM). A congruence class from the N-way associative directory including a...
5745730 Apparatus and methods for implementing dedicated cache flushing  
A bus interface is connected to a system bus for monitoring a bus command indicating that data is updated on a cache memory of a processor. If the data is updated on the cache memory, the external...
5742791 Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor  
A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction...
5737568 Method and apparatus to control cache memory in multiprocessor system utilizing a shared memory  
In a multiprocessor system having a shared memory containing the state of the data for every entry in each cache memory possessed by each processor. The state of the data is set to a "shared state"...
5737756 Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue  
A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to...
5724550 Using an address pin as a snoop invalidate signal during snoop cycles  
A circuit for responding to a microprocessor-generated write of a write-protected area of memory by invalidating a cache line corresponding to a write address in a microprocessor's internal cache...
5708792 Method and apparatus for a coherent copy-back buffer in a multipressor computer system  
A method and apparatus for maintaining cache coherency in a multiprocessor system having a plurality of processors and a shared main memory. Each of the plurality of processors is coupled to at...
5706463 Cache coherent computer system that minimizes invalidation and copyback operations  
A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache...
5706464 Method and system for achieving atomic memory references in a multilevel cache data processing system  
Atomic memory references require a data processing system to present the appearance of a coherent memory system, which may be achieved in most multiprocessor systems by means of normal memory...
5701437 Dual-memory managing apparatus and method including prioritization of backup and update operations  
According to this invention, a dual-memory managing apparatus is applied to a system in which a plurality of memories and a plurality of processors are connected to each other through a data bus,...
5699552 System for improved processor throughput with enhanced cache utilization using specialized interleaving operations  
A system for interleaving invalidation cycles to a cache memory during those periods when the processor is waiting or has not need to access cache memory. These periods occur during a Read-Miss...
5696937 Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses  
A state machine system is used to control a cache controller in a network involving the operations of a processor having a store-through cache and operations involving an invalidation queue which...
5696935 Multiported cache and systems  
A cache memory is provided with a plurality of address ports and a corresponding plurality of tag ports for use with multiple pipes in a pipelined system. One of the address ports is dedicated to...
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