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6003106 |
DMA cache control logic
A method and apparatus for snooping a host bridge. In a preferred embodiment, the apparatus includes a mechanism for loading data into the host bridge. Once the data is loaded, it is determined...
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5996050 |
Cache coherency detection in a bus bridge verification system
A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address...
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5991847 |
Data pattern caching for speeding up write operations
A data pattern cache stores data patterns in units (i.e., a sector). A given data pattern is associated with one or more physical device address ranges which store such data pattern (e.g.,...
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5991855 |
Low latency memory read with concurrent pipe lined snoops
A method processes memory transactions in a computer system having a system memory and a cache memory. The method transmits a memory request to the system memory without waiting for the cache...
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5983024 |
Method and apparatus for robust data broadcast on a peripheral component interconnect bus
A method of robust data broadcasting on a peripheral component interconnect(PCI) bus sets intended target agents to snoop the broadcast transaction in which the master agent also responds as the...
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5983325 |
Dataless touch to open a memory page
A computer system supports a touch command which may be used to open a page in the main memory. Microprocessors within the computer system may determine an appropriate time at which to perform the...
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5978874 |
Implementing snooping on a split-transaction computer system bus
Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data...
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5978886 |
Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache
An apparatus and method for duplicating tag addresses to maintain addresses of central processing unit (CPU) data stored in write buffers external to a cache are disclosed. Advance notification of...
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5974511 |
Cache subsystem with pseudo-packet switch
A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus...
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5966729 |
Snoop filter for use in multiprocessor computer systems
An improved method and apparatus for distributing transactions among a plurality of groups of processors in a multiprocessor computer system are disclosed. An embodiment of the invention includes...
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5966728 |
Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device
A computer system and method allow memory locations in both system memory and expansion memory devices coupled to an input/output (I/O) bus to be cacheable in a central processing unit (CPU) cache....
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5961621 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it...
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5963978 |
High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators
A high-level (L2) cache and a efficient method for writing directory entries into an array of directory entries are disclosed. The high-level (L2) cache operates differently depending upon whether...
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5960457 |
Cache coherency test system and methodology for testing cache operation in the presence of an external snoop
A test methodology for a cache memory subsystem includes setting a test unit to initiate a snoop cycle on a local bus upon lapse of a predetermined delay. The predetermined delay is initially set...
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5946709 |
Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a...
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5941968 |
Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
A computer system is provided including a CPU, a graphics controller, system memory, data steering logic, a DMA controller and arbitration logic. The graphics controller and system memory are...
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5943685 |
Method of shared intervention via a single data provider among shared caches for SMP bus
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the...
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5943686 |
Multiple cache directories for non-arbitration concurrent accessing of a cache memory
A method of accessing a cache used by a processor of a computer system, to eliminate arbitration logic which would otherwise be required to handle operations from multiple snooping devices. A...
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5930821 |
Method and apparatus for shared cache lines in split data/code caches
An apparatus and method for sharing cache lines within a split data/code cache is provided. The invention utilizes cache snoop and state control, coupled to both a data cache and a code cache,...
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5930483 |
Method and apparatus for communications control on a small computer system interface
A method and apparatus are provided for controlling communications on a small computer system interface (SCSI). A cache memory is arranged for storing an input queue, a status queue and a cache...
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5926830 |
Data processing system and method for maintaining coherency between high and low level caches using inclusive states
A data processing system and method for maintaining coherency between a high-level (L2) cache and a low-level (L1) cache are disclosed. The L2 (high-level) cache operates in a first mode of...
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5920891 |
Architecture and method for controlling a cache memory
A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory...
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5920892 |
Method and system for inhibiting transfer of duplicate write addresses in multi-domain processor systems with cross-bus architecture to reduce cross-invalidation requests
A two domain digital network with each domain having its own system bus and its own bus exchange module permits Write operation addresses to be passed between domains. Each bus exchange module...
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5918069 |
System for simultaneously writing back cached data via first bus and transferring cached data to second bus when read request is cached and dirty
A bus bridge mutually connects a CPU bus to which a CPU and a corresponding cache memory having a write-back scheme are coupled, an I/O bus to which a bus master is coupled, and a main memory which...
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5915124 |
Method and apparatus for a first device accessing computer memory and a second device detecting the access and responding by performing sequence of actions
A method of controlling an input/output (I/O) device connected to a computer to facilitate fast I/O data transfers. An address space for the I/O device is created in the virtual memory of the...
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5913226 |
Snoop cache memory control system and method
To implement a system minimizing access to the shared memory, the previous owner number storage module contains the number of a cache memory or the shared memory which was the previous owner of...
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5909699 |
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the...
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5907853 |
Method and apparatus for maintaining duplicate cache tags with selectable width
A multiprocessor computer architecture containing processor caches that are kept coherent, and in particular, a duplicate cache tag subsystem and method for maintaining duplicate cache tags, are...
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5905876 |
Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the...
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5905999 |
Cache sub-array arbitration
A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in...
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5905998 |
Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system
A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache...
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5903908 |
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache...
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5901326 |
Memory bus address snooper logic for determining memory activity without performing memory accesses
A parallel multiprocessor data processing system having a plurality of nodes for processing data and a switch connected to each of said nodes for switching messages between the nodes, each node...
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5900016 |
System for using a cache memory with a write-back architecture
A computer system includes a microprocessor, a cache memory, main memory and supporting logic. The supporting logic includes cache control logic that determines whether an access to memory results...
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5898892 |
Computer system with a data cache for providing real-time multimedia data to a multimedia engine
A computer system and method optimized for real-time multimedia applications are presented. The computer system, including a dedicated multimedia engine coupled directly to a real-time data cache,...
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5895488 |
Cache flushing methods and apparatus
Methods and apparatus for managing a cache which includes a number of dirty lines in which (a) the percentage of dirty lines in the cache is determined, (b) the cache is flushed if the determined...
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5893921 |
Method for maintaining memory coherency in a computer system having a cache utilizing snoop address injection during a read transaction by a dual memory bus controller
A method for maintaining memory coherency in a data processing system is disclosed. The data processing system includes a memory system having a dual bus memory controller, which is coupled to a...
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5893151 |
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
An apparatus for maintaining cache coherency for snoop operations includes a processor core for fetching, decoding, and executing instructions, a data cache coupled to the processor core for...
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5893098 |
System and method for obtaining and collating survey information from a plurality of computer users
A system for obtaining information from a plurality of computer users (7 to 12), comprising a processing apparatus (2) including an input mechanism (3 and 4) via which a survey author may input...
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5893145 |
System and method for routing operands within partitions of a source register to partitions within a destination register
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional...
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5881303 |
Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode
A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order presented by that subnode. Therefore,...
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5875462 |
Multi-processor data processing system with multiple second level caches mapable to all of addressable memory
A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each...
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5860114 |
Method and apparatus for managing snoop requests using snoop advisory cells
A plurality of "snoop advisory" bits are maintained by snoop management circuitry externally to the processor structure. Each snoop advisory bit corresponds to a respective "snoop advisory page" of...
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5860109 |
Methods and apparatus for a coherence transformer for connecting computer system coherence domains
An apparatus for facilitating the sharing of memory blocks, which has local physical addresses at a computer node, between the computer node and an external device. The apparatus includes snooping...
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5860112 |
Method and apparatus for blending bus writes and cache write-backs to memory
Apparatus and a method for utilizing a memory bus write buffer to blend up-to-date data stored in a processor cache and being written back to memory with data in the write buffer being written to...
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5845324 |
Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access
A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system...
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5845327 |
Cache coherency where multiple processors may access the same data over independent access paths
The present invention, generally speaking, provides a hardware graphics accelerator for use in a computer system having a data processor, a system bus, and a memory subsystem including both main...
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5832276 |
Resolving processor and system bus address collision in a high-level cache
A L2 cache for resolving collisions between processor request originating from a processor and system request originating from a computing unit attached to the system bus is provided. First, the L2...
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5829040 |
Snooper circuit of a multi-processor system
A snooper circuit of a multi-processor system includes a plurality of processor boards each having a central processing unit, a cache memory, a cache controller to control the cache memory and a...
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5829034 |
Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains
A coherence transformer for allowing a computer node and one or more external devices to share memory blocks having local physical addresses at a memory module of the computer node. The coherence...
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