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9037804 Efficient support of sparse data structure access  
Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field indicating the size of usable data stored...
9015436 Performing an atomic operation without quiescing an interconnect structure  
In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a...
9003130 Multi-core processing device with invalidation cache tags and methods  
A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated...
8994740 Cache line allocation method and system  
A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of...
8996810 System and method of detecting cache inconsistencies  
A system and method of detecting cache inconsistencies among distributed data centers is described. Key-based sampling captures a complete history of a key for comparing cache values across data...
8996837 Providing multi-tenancy within a data storage apparatus  
A technique provides multi-tenancy within a data storage apparatus. The technique involves dividing, by processing circuitry, storage units of the data storage apparatus into multiple groups of...
8990506 Replacing cache lines in a cache memory based at least in part on cache coherency state information  
In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the...
8977818 Combined transparent/non-transparent cache  
In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a...
8966193 Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts sensor  
Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be...
8953354 Semiconductor memory device and method of driving semiconductor memory device  
A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural...
8954691 Identifying unallocated memory segments  
A network device that includes a first memory to store packets in segments; a second memory to store pointers associated with the first memory; a third memory to store summary bits and allocation...
8949539 Conditional load and store in a shared memory  
A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of...
8930634 Speculative read in a cache coherent microprocessor  
A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent...
8930628 Managing in-line store throughput reduction  
Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At...
8930657 Method and apparatus for realtime detection of heap memory corruption by buffer overruns  
One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic...
8930637 Arrangement  
An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part...
8924653 Transactional cache memory system  
A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an...
8924644 Extending cache in a multi-processor computer  
Methods, apparatuses, and computer program products of extending cache in a multi-processor computer are provided. Embodiments include detecting, by a donor processor, nonuse of a donor...
8924817 Method and apparatus for calculating error correction codes for selective data updates  
The present invention provides a method and apparatus for selectively updating error correction code bits. One embodiment of the method includes determining a first subset of a plurality of error...
8909872 Computer system with coherent interconnection  
A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is...
8904174 System, method and computer program product for product license management  
According to one aspect of the present disclosure, a method and technique for product license management for a clustered environment having a plurality of nodes is disclosed. The method includes...
8898395 Memory management for cache consistency  
Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an...
8880805 Computer system having cache subsystem performing demote requests  
Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a...
8874851 Systems and methods for intelligent content aware caching  
Methods and systems to intelligently cache content in a virtualization environment using virtualization software such as VMWare ESX or Citrix XenServer or Microsoft HyperV or Redhat KVM or their...
8874934 Nonvolatile memory device and operating method  
Disclosed is an operating method of a non-volatile memory device which comprises randomizing data to store the randomized data; erasing the randomized data; and outputting erase data according to...
8868845 Dynamic single/multi-reader, single-writer spinlocks  
Example embodiments of the present invention include a method, system and computer program product for managing spinlocks in a multi-core computer system. The method comprises providing a spinlock...
8862830 Caching data objects on a client side using a prototype chain  
Provided are a computer implemented method, computer program product, and system for caching a data object. A copy of an original data object to a specified depth is obtained. The copy of the...
8856457 Information processing system and a system controller  
In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache...
8838906 Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution  
In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory,...
8838939 Debugging multithreaded code by generating exception upon target address CAM search for variable and checking race condition  
Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system,...
8838908 Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM  
A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated...
8825962 Push-based cache invalidation notification  
In one embodiments, one or more first computing devices receive updated values for user data associated with a plurality of users; and for each of the user data for which an updated value has been...
8819352 Hybrid Transactional Memory (HybridTM)  
Embodiments related to a hardware transactional memory (HTM). An aspect includes setting a mode register of a processor core of a computer to indicate a HTM mode. Another aspect includes executing...
8819357 Method and system for ensuring cache coherence of metadata in clustered file systems  
Metadata of a shared file in a clustered file system is changed in a way that ensures cache coherence amongst servers that can simultaneously access the shared file. Before a server changes the...
8812796 Private memory regions and coherence optimizations  
Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory...
8812786 Dual-granularity state tracking for directory-based cache coherence  
A system and method of providing directory cache coherence are disclosed. The system and method may include tracking the coherence state of at least one cache block contained within a region using...
8806147 System and method for creating ordering points  
A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data...
8806146 Method and system to accelerate address translation  
In a method to accelerate address translation into a physical address, a computer maps a virtual memory area with a large page, the virtual memory area including multiple virtual pages satisfying...
8806145 Methods and apparatuses for improving speculation success in processors  
Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality...
8799582 Extending cache coherency protocols to support locally buffered data  
A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated...
8799581 Cache coherence monitoring and feedback  
Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads...
8799396 Method and system for an efficient distributed cache with a shared cache repository  
Network cache systems are used to improve network performance and reduce network traffic. An improved network cache system that uses a centralized shared cache system is disclosed. Each cache...
8793327 Grid computing space  
A method and apparatus for using a tree-structured cluster as a library for a computing grid. In one embodiment, a request for computation is received at a cache node of the cluster. The...
8793439 Accelerating memory operations using virtualization information  
A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under...
8782344 Systems and methods for managing cache admission  
A cache layer leverages a logical address space and storage metadata of a storage layer (e.g., storage layer) to cache data of a backing store. The cache layer maintains access metadata to track...
8782347 Controllably exiting an unknown state of a cache coherency directory  
In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message...
8769212 Memory model for hardware attributes within a transactional memory system  
A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test...
8762651 Maintaining cache coherence in a multi-node, symmetric multiprocessing computer  
Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first...
8756379 Managing concurrent accesses to a cache  
Various embodiments of the present invention allow concurrent accesses to a cache. A request to update an object stored in a cache is received. A first data structure comprising a new value for...
8751751 Method and apparatus for minimizing cache conflict misses  
A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided....