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7624126 |
Registering for and retrieving database table change information that can be used to invalidate cache entries
A server provides Web responses that can include content from data tables in a database. The server maintains a cache (e.g., in system memory) that can store content (including content from data...
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7620779 |
System and method for handling direct memory accesses
Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop...
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7620778 |
Low power microprocessor cache memory and method of operation
Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and...
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7620687 |
Distributed request routing
A plurality of servers for processing client requests forward the requests among themselves to achieve a balanced load. When a server initially receives a client request, it randomly selects...
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7617372 |
Avoiding copy on first write
Handling a write operation to write data to a section of a storage device includes determining if the section needs to be copied to at least a first target device and, if the section of the storage...
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7613886 |
Methods and apparatus for synchronizing data access to a local memory in a multi-processor system
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
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7613884 |
Multiprocessor system and method ensuring coherency between a main memory and a cache memory
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a...
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7610448 |
Obscuring memory access patterns
For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is...
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7606980 |
Demand-based error correction
A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error...
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7606978 |
Multi-node computer system implementing global access state dependent transactions
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to...
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7603524 |
Method and apparatus for filtering snoop requests using multiple snoop caches
A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop...
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7603026 |
Information processing method and information processing apparatus
This invention provides an information processing method and apparatus, which can set all extent sizes of data divisionally recorded on a disk to be equal to or larger than the minimum recording...
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7600152 |
Configuring cache memory from a storage controller
Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first...
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7600079 |
Performing a memory write of a data unit without changing ownership of the data unit
A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory...
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7596665 |
Mechanism for a processor to use locking cache as part of system memory
The present invention provides a mechanism for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or...
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7594145 |
Improving performance of a processor having a defective cache
In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The...
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7584331 |
Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout
In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first...
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7584330 |
Multi-processor data coherency
A method for maintaining coherent data in a multiprocessor system having a plurality of processors coupled to main memory, where each processor has an internal cache which is externally unreadable...
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7584329 |
Data processing system and method for efficient communication utilizing an Ig coherency state
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache...
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7581067 |
Load when reservation lost instruction for performing cacheline polling
A load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a...
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7581065 |
Low locality-of-reference support in a multi-level cache hierachy
A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains...
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7581064 |
Utilizing cache information to manage memory access and cache utilization
In a method of utilizing cache metadata to optimize memory access, cache metadata associated with a set of cache locations is inspected by software. The cache metadata is analyzed to determine...
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7581025 |
System and method for synchronizing copies of data in a computer system
An improved synchronization system and method for copies of data in a computer system. The computer system comprises a cluster, wherein each computer in the cluster may store a local copy of a data...
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7577795 |
Disowning cache entries on aging out of the entry
Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the...
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7577791 |
Virtualized load buffers
A memory addressing technique using load buffers is described. More particularly, embodiments of the invention relate to a method and apparatus for accessing data in a computer system by exploiting...
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7577015 |
Memory content inverting to minimize NTBI effects
In general, in one aspect, the disclosure describes an apparatus that includes a memory device having a plurality of memory cells. An inverter is used to invert data and tag information destined...
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7574572 |
Cache memory, system, and method of storing data
A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data...
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7571285 |
Data classification in shared cache of multiple-core processor
In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class...
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7565490 |
Out of order graphics L2 cache
Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that...
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7558923 |
Prevention of live-lock in a multi-processor system
Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and...
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7555611 |
Memory management of local variables upon a change of context
A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java...
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7552286 |
Performance of a cache by detecting cache lines that have been reused
A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate...
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7549025 |
Efficient marking of shared cache lines
One embodiment of the present invention provides a system that efficiently marks cache lines in a multi-processor computer system. The system starts by receiving a load request for a cache line...
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7546420 |
Efficient trace cache management during self-modifying code processing
Efficient trace cache management during self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache...
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7543116 |
Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains
A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target...
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7529888 |
Software caching with bounded-error delayed update
In some embodiments, the invention involves a system and method relating to software caching with bounded-error delayed updates. Embodiments of the present invention describe a delayed-update...
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7526611 |
Unified processor cache model in multiprocessor system
Exemplary embodiments include a multiprocessor system including: a plurality of processors in operable communication with an address manager and an memory controller; and a unified cache in...
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7523267 |
Method for ensuring fairness among requests within a multi-node computer system
A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest...
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7523266 |
Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level
One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor....
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7519775 |
Enforcing memory-reference ordering requirements at the L2 cache level
One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein...
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7519774 |
Data processor having a memory control unit with cache memory
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
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7509461 |
Method and apparatus for intelligent buffer cache pre-emption
The present invention augments each entry in a memory frame table to include information associated with the availability of any page that is buffer cache allocated. The availability information...
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7506107 |
Shared memory multiprocessor system
In a shared memory multiprocessor system, data reading accesses and data write-back completion notifications are selected in synchronism with all of the nodes to order them. In each of the nodes, a...
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7502894 |
Shared rowset
Multiple Shared Rowsets, can access rows of data stored in a Cached Rowset independently. These Shared Rowsets can have their own cursor, sorted order, filtered rows, and pending changes.
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7502893 |
System and method for reporting cache coherency state retained within a cache hierarchy of a processing node
A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to...
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7500065 |
Data processing system and method for efficient L3 cache directory management
A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state...
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7500064 |
Data coherence system
A data coherence system includes a generation number written to a data track of a logical sub-system. The generation number is compared to a corresponding generation number in a processing device...
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7496726 |
Controlling contention via transactional timers among conflicting transactions issued by processors operating in insistent or polite mode
A system for controlling contention between conflicting transactions in a transactional memory system. During operation, the system receives a request to access a cache line and then determines if...
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7496715 |
Programmable cache management system and method
A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored...
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7493453 |
System, method and storage medium for prefetching via memory block tags
A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory...
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