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6912669 |
Method and apparatus for maintaining cache coherency in a storage system
A method and apparatus for cache coherency in storage system is disclosed. The invention maintains cache coherency in the controller system of the storage system in a manner to minimize the...
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6912562 |
Cache invalidation technique with spurious resource change indications
A Web server maintains, for one or more resources, a respective list of clients who requested that resource. The server takes on the responsibility of notifying all of those clients on when the...
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6904502 |
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In...
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6901450 |
Multiprocessor machine and cache control method for providing higher priority to shared cache that is accessed by multiprocessors
In multiprocessor machines and chip multiprocessor systems in particular, the object of the present invention is to reduce data communication between the LSI chip and external components and to...
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6901483 |
Prioritizing and locking removed and subsequently reloaded cache lines
A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special...
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6892277 |
System and method for optimizing remote data content distribution
The present invention discloses a system and method for optimizing remote data distribution. A system and method for optimizing remote data includes receiving a request for content at a first...
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6886079 |
Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (NUMA) computer system
A non-uniform memory access (NUMA) computer system includes at least one remote node and a home node coupled by a node interconnect. The home node contains a home system memory and a memory...
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6877030 |
Method and system for cache coherence in DSM multiprocessor system without growth of the sharing vector
The present invention is directed to a method and a system for maintaining cache coherence in a distributed shared memory (DSM) multiprocessor system. The method begins with a receiving of a shared...
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6877029 |
Method and apparatus for managing node controllers using partitions in a computer system
A partitioned computer system ( 32 ) includes a plurality of node controllers ( 12 ) connected by a network ( 14 ) and partitioned into a plurality of partitioned groups ( 40 ). A requesting node...
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6877067 |
Shared cache memory replacement control method and apparatus
In a multiprocessor system in which a plurality of processors share an n-way set-associative cache memory, a plurality of ways of the cache memory are divided into groups, one group for each...
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6871259 |
File system including non-volatile semiconductor memory device having a plurality of banks
A flash memory includes a data bank having a plurality of banks, a merge bank, and an update data bank. A file system using the flash memory includes a unit storing update data corresponding to a...
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6871267 |
Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency
A multi-processor system includes a system bus communicating between processors, and a bus arbiter. Responsive to a cache line invalidation command, a processor cache conditionally casts back the...
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6868485 |
Computer system with integrated directory and processor cache
A computer system with an integrated directory and processor cache. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than...
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6859863 |
Method and system for managing data at an input/output interface for a multiprocessor system
A multiprocessor system and method includes a processing sub-system including a plurality of processors and a processor memory system. A network is operable to couple the processing sub-system to...
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6857051 |
Method and apparatus for maintaining cache coherence in a computer system
The computer system includes a processor having an associated cache to store a data segment in a Read Only state. For one embodiment, a Read Only state may indicate that no other processor of the...
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6851035 |
Method and apparatus for storing data packets with a packet boundary indicator
An apparatus for storing packets. The apparatus includes a memory for holding packets. The apparatus includes a mechanism for storing at least two packets in the memory with only one packet...
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6848035 |
Semiconductor device with multi-bank DRAM and cache memory
A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM...
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6842824 |
Cache control program and computer for performing cache processes utilizing cache blocks ranked according to their order of reuse
A cache control program that maintains a high cache hit ratio even in the case of a file of large size being accessed. A computer that executes the cache control program judges whether transferred...
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6842822 |
System and method for cache external writing
A system ( 10 ) uses shared resources ( 44, 54 ) to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (...
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6839812 |
Method and system to cache metadata
Briefly, in accordance with an embodiment of the invention, a method and system to store cache metadata from a higher latency media in a lower latency media is provided.
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6839806 |
Cache system with a cache tag memory and a cache tag buffer
A cache system comprising a cache tag buffer 270 for storing a part of a cache tag memory 260 . When a memory processing request is issued from a processor 10 , a cache control means 280 ...
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6839813 |
TLB operations based on shared bit
A digital system and method of operation is provided in which several processing resources ( 340 ) and processors ( 350 ) are connected to a shared translation lookaside buffer (TLB) ( 300, 310 ( n...
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6836829 |
Peripheral device interface chip cache and data synchronization method
A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The...
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6836826 |
Multilevel cache system and method having a merged tag array to store tags for multiple data arrays
A multilevel cache system and method. A first data array and a second data array are coupled to a merged tag array. The merged tag array stores tags for both the first data array and second data...
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6834327 |
Multilevel cache system having unified cache tag memory
A unified tag subsystem for a multilevel cache memory system. The unified tag subsystem receives a cache line address including a tag index portion, a high order part and an optional cache line...
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6832297 |
Method and apparatus for managing data in a distributed buffer system
A method, apparatus, and computer implemented instructions for managing a plurality of caches of data, wherein the data processing system includes a plurality of independent computers. In response...
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6829682 |
Destructive read architecture for dynamic random access memories
A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an...
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6829681 |
Cache system which performs cache flash upon emergency and dual system
A dual system includes a 0-subsystem and a 1-subsystem, each of which in turn includes a first bus, a second bus, a main memory having a memory section reading from and writing into which is...
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6826669 |
Multi-protocol memory lookup system and method
A memory system includes a memory array for storing a plurality of data elements, the memory array comprising a plurality of memory blocks. In one embodiment, the data element are tag string data....
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6826651 |
State-based allocation and replacement for improved hit ratio in directory caches
A system and method of maintaining consistent cached copies of memory in a multiprocessor system having a main memory, includes a memory directory having entries mapping the main memory, an access...
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6826656 |
Reducing power in a snooping cache based multiprocessor environment
A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache...
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6820047 |
Method and system for simulating an operation of a memory
A simulation system simulates an operation of a memory. This system includes an error generating step in addition to a memory operation simulating step. An error can easily be generated in a...
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6816960 |
Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution
A vector artchitecture processing unit according to the present invention comprises a vector scatter (VSC) address coincidence detection unit 3 that comprises registers in which an area start...
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6810466 |
Microprocessor and method for performing selective prefetch based on bus activity level
A microprocessor that selectively performs prefetch instructions based upon an indication of future processor bus activity and cache line status. The microprocessor includes a programmable...
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6810467 |
Method and apparatus for centralized snoop filtering
An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and...
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6807619 |
Advancing bank pointer in prime numbers unit
The cache arrangement includes a cache that may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot...
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6804750 |
Technique for reducing memory latency during a memory request
A technique for reducing the latency associated with a memory read request. A bypass path is provided to direct the address of a corresponding request to a memory controller. The memory controller...
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6801984 |
Imprecise snooping based invalidation mechanism
A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided...
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6795900 |
Method and system for storing data at input/output (I/O) interfaces for a multiprocessor system
A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an...
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6792498 |
Memory system with mechanism for assisting a cache memory
Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a...
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6792512 |
Method and system for organizing coherence directories in shared memory systems
A method and structure for a “dynamic CCR/sparse directory implementation,” includes maintaining state information of the main memory cached in the shared caches of the other compute nodes,...
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6792508 |
Cache with multiple fill modes
A cache architecture ( 16 ) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory ( 20 ). The RAM set cache can be used in conjunction with other...
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6789172 |
Cache and DMA with a global valid bit
A digital system has at least one processor, with an associated multi-segment cache memory circuit. A single global validity circuit (VIG) is connected to the memory circuit and is operable to...
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6785774 |
High performance symmetric multiprocessing systems via super-coherent data mechanisms
A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that,...
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6785776 |
DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism
A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system...
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6785777 |
Control logic for memory modification tracking with hierarchical dirty indicators
A dirty memory that includes dirty indicators settable to indicate dirtied pages of memory is provided with control logic operable automatically to interrogate the dirty memory to identify dirty...
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6785763 |
Efficient memory modification tracking with hierarchical dirty indicators
A dirty memory for a computer system is configured hierarchically. This provides for more rapid identification of pages of memory that have been dirtied and require attention. For example for the...
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6785778 |
Share masks and alias for directory coherency
A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of...
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6785714 |
System and method for employing slot level locking of a cache
A system and method for employing slot level cache locking are disclosed. When a rich media file request occurs, a general lock is put on the cache to determine whether the file has already been...
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6782456 |
Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism
A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands...
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