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7093081 |
Method and apparatus for identifying false cache line sharing
A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a...
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7089374 |
Selectively unmarking load-marked cache lines during transactional program execution
One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are...
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7089375 |
Device and method for configuring a cache tag in accordance with burst length
In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not functioning properly. In addition, the burst...
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7089371 |
Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory
A microprocessor apparatus for exclusive prefetch and initialization of cache lines, including translation logic and execution logic. The translation logic translates a block allocate and...
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7089296 |
System and method for caching and validating user and command specific server response messages
A system and method is provided for user and command specific place based caching with cache validation, including a server; a database; a server cache; the server responsive to receiving a request...
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7089372 |
Local region table for storage of information regarding memory access by other nodes
Information regarding memory access by other nodes within a coherency controller of a node is locally stored. The coherency controller receives a transaction relating a line of local memory of the...
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7089397 |
Method and system for caching attribute data for matching attributes with physical addresses
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
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7089362 |
Cache memory eviction policy for combining write transactions
Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines...
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7089376 |
Reducing snoop response time for snoopers without copies of requested data via snoop filtering
In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering...
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7089368 |
Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory
A microprocessor apparatus for exclusive prefetch of a block of data from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended block...
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7089357 |
Locally buffered cache extensions having associated control parameters to determine use for cache allocation on subsequent requests
A method and apparatus for cache management in a data storage system is presented. A table with tags corresponding to cache slots in a cache memory is provided. A copy of the table is stored in a...
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7089365 |
Method and system for an atomically updated, central cache memory
Disclosed is a central cache that is updated without the overhead of locking. Updates are “atomic” in that they cannot be interrupted part way through. Applications are always free to read data...
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7085897 |
Memory management for a symmetric multiprocessor computer system
A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local...
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7082500 |
Optimized high bandwidth cache coherence mechanism
A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A...
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7082501 |
Remote node accessing local memory by using distributed shared memory
A DSM system includes a local node, a first remote node, and a second remote nodes. The data access method for a remote node to access a local node in the DSM system includes the steps of directly...
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7080207 |
Data storage apparatus, system and method including a cache descriptor having a field defining data in a cache block
A system, method and apparatus for providing and utilizing a storage cache descriptor by a storage controller are disclosed which provide the ability to effectively balance the size of storage...
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7080210 |
Microprocessor apparatus and method for exclusive prefetch of a cache line from memory
A microprocessor apparatus that enables exclusive prefetch of a cache line from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended...
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7076608 |
Invalidating cached data using secondary keys
A system and method for facilitating the invalidation of cached data, in which the data to be invalidated are identified using information other than a primary key. The primary key for a cached...
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7076613 |
Cache line pre-load and pre-own based on cache coherence speculation
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor...
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7076597 |
Broadcast invalidate scheme
A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a...
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7076614 |
System and method for optimizing bus bandwidth utilization by grouping cache write-backs
A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by...
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7073026 |
Microprocessor including cache memory supporting multiple accesses per cycle
A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a...
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7073043 |
Multiprocessor system supporting multiple outstanding TLBI operations per partition
Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete...
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7073030 |
Method and apparatus providing non level one information caching using prefetch to increase a hit ratio
A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1...
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7069384 |
System and method for cache external writing and write shadowing
A system ( 10 ) uses shared resources ( 44, 54 ) to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (...
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7065613 |
Method for reducing access to main memory using a stack cache
The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to...
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7062611 |
Dirty data protection for cache memories
A method is described for protecting dirty data in cache memories in a cost-effective manner. When an instruction to write data to a memory location is received, and that memory location is being...
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7062612 |
Updating remote locked cache
A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is...
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7055006 |
System and method for blocking cache use during debugging
A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also...
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7051166 |
Directory-based cache coherency scheme for reducing memory bandwidth loss
A memory system employing a directory-based cache coherency scheme comprises a memory unit, a data bus, a plurality of information buses, and a memory controller. The memory unit comprises a...
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7051159 |
Method and system for cache data fetch operations
A cache controller structure and method are provided for managing cache access for a computer system. The computer system has a processor having a direction flag and configured to run a repetitive...
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7047363 |
Cache memory and control method thereof
A cache memory related to the present invention is a cache memory employing a set associative system, for generating a valid bit for showing the presence of validity of a cache data, and comprises...
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7043609 |
Method and apparatus for protecting a state associated with a memory structure
A method for protecting reliability of data associated with a data array is provided. The method initiates with defining state information associated with the data array. Then, crucial state...
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7043610 |
System and method for maintaining cache coherency without external controller intervention
A disk array includes a system and method for cache management and conflict detection. Incoming host commands are processed by a storage controller, which identifies a set of at least one cache...
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7035979 |
Method and apparatus for optimizing cache hit ratio in non L1 caches
A method and apparatus for increasing the performance of a computing system and increasing the hit ratio in at least one non-L1 cache. A caching assistant and a processor are embedded in a...
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7035981 |
Asynchronous input/output cache having reduced latency
The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication...
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7028144 |
Method and apparatus for an in-situ victim cache
A method and apparatus for a microprocessor with a cache that has the advantages given by a victim cache without physically having a victim cache is disclosed. In one embodiment, a victim flag may...
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7028150 |
Arrangement of data within cache lines so that tags are first data received
A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each...
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7028151 |
Information processing device equipped with improved address queue register files for cache miss
When an input address AD is previously stored in a register 211 , if a matching signal EQ 1 is active, then an address queue control circuit 19 A latches an offset of the input address AD into a...
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7024521 |
Managing sparse directory evictions in multiprocessor systems via memory locking
Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache...
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7020752 |
Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory unit
In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at...
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7020746 |
Method and system for an atomically updated, central cache memory
Disclosed is a central cache that is updated without the overhead of locking. Updates are “atomic” in that they cannot be interrupted part way through. Applications are always free to read data...
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7017014 |
Method, system and program product for maintaining data consistency across a hierarchy of caches
A method, system and program product maintains consistency of data across a hierarchy of caches. Under the present invention, each data entry in the hierarchy of caches is assigned its own...
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7012612 |
Context dependent image caching
A mechanism is provided that identifies certain classes of images that are likely to be re-used, and utilizes this information to manage a cache better. This may include flushing certain classes of...
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7010648 |
Method and apparatus for avoiding cache pollution due to speculative memory load operations in a microprocessor
A cache pollution avoidance unit includes a dynamic memory dependency table for storing a dependency state condition between a first load instruction and a sequentially later second load...
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7003632 |
Method and apparatus for scalable disambiguated coherence in shared storage hierarchies
Scalable disambiguating accesses in multi-level cache hierarchies provides for improved system performance and reduced cost. Shared-storage provides portions to hold data and portions to hold...
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7003631 |
System having address-based intranode coherency and data-based internode coherency
A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is...
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6996675 |
Retrieval of all tag entries of cache locations for memory address and determining ECC based on same
The retrieval of all tag entries of cache locations for a memory address is disclosed, as well as the determining of an error correcting code (ECC) for the tag entries based thereon. Tag entries of...
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6996689 |
Systems and methods for striped storage migration
Systems and methods for expanding capacity of a storage system are provided. Data blocks of a capacity increasing disk are pre-configured with a first progress indicator used to determine correctly...
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6993631 |
L2 cache maintaining local ownership of remote coherency blocks
A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first...
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