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7233976 Cache slot lock for multi-thread file request  
System and method for employing slot level cache locking are disclosed. When a rich media file request occurs, a general lock is put on the cache to determine whether the file has already been...
7234028 Power/performance optimized cache using memory write prevention through write snarfing  
A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or...
7228386 Programmably disabling one or more cache entries  
A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be...
7225299 Supporting speculative modification in a data cache  
Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator...
7216204 Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment  
Stored units of information related to packet processing are associated with identifiers, each of which is maintained as an entry in a Content Addressable Memory (CAM). Each entry includes status...
7216202 Method and apparatus for supporting one or more servers on a single semiconductor chip  
One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to...
7216188 Techniques for accessing devices through a set of serial buses automatically setting unique enclosure addresses and detecting non-unique enclosure addresses upon initialization  
In a system including multiple enclosures, unique enclosure addresses can be set automatically via software. The enclosure addresses may be stored in non-volatile memory within the enclosures. In a...
7210006 Computer system supporting read-to-write-back transactions for I/O devices  
A read-to-write-back transaction may allow I/O subsystems (or other devices) to perform a write to a portion of a cache block without gaining ownership of the cache block and requiring that it...
7206903 Method and apparatus for releasing memory locations during transactional execution  
One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during...
7197605 Allocating cache lines  
Allocating cache lines includes incurring a cache write miss and, after incurring the cache write miss, writing data having a memory address to a cache line that does not include data at the memory...
7194586 Method and apparatus for implementing cache state as history of read/write shared data  
A method and apparatus are provided for implementing a cache state as history of read/write shared data for a cache in a shared memory multiple processor computer system. An invalid temporary state...
7194587 Localized cache block flush instruction  
A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending...
7191289 Method and system for an atomically updated, central cache memory  
Disclosed is a central cache that is updated without the overhead of locking. Updates are “atomic” in that they cannot be interrupted part way through. Applications are always free to read data...
7188217 Embedded DRAM cache memory and method having reduced latency  
A computer system includes a processor, a system memory, and an integrated circuit system controller coupled to the processor and the system memory. The system controller includes a system memory...
7181576 Method for synchronizing a cache memory with a main memory  
Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each...
7177983 Managing dirty evicts from a cache  
In a Constant Access Time Bounded (CATB) cache, if a dirty line in a search group of the cache is selected for eviction from the cache, marking the dirty line as evicted, selecting a replacement...
7177986 Direct access mode for a cache  
A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may...
7177987 System and method for responses between different cache coherency protocols  
Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency...
7171520 Cache flush system and method thereof  
The present invention relates to a cache flush system and the method for a cache flush performed in cache memory against at least one corresponding prescribed event in a multi-processor system....
7171522 Storage system including storage adaptors having cache memories and grasping usage situation of each cache memory and equalizing usage of cache memories  
A storage system having a cluster configuration that prevents a load from concentrating on a certain storage node and enhances access performance is disclosed. The storage system is provided with...
7171540 Object-addressed memory hierarchy that facilitates accessing objects stored outside of main memory  
One embodiment of the present invention provides an object-addressed memory hierarchy that is able to access objects stored outside of main memory. During operation, the system receives a request...
7171666 Processor module for a multiprocessor system and task allocation method thereof  
A multiprocessor system includes a plurality of processor modules having a detector for detecting accesses by respective tasks to data shared among cache memories in the processor modules. Also...
7167952 Method and system for performing a memory-mode write to cache  
A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent,...
7165144 Managing input/output (I/O) requests in a cache memory system  
Provided are a method, system, and program for managing Input/Output (I/O) requests in a cache memory system. A request is received to data at a memory address in a first memory device, wherein...
7162589 Methods and apparatus for canceling a memory data fetch  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for transmitting...
7159076 Cache operation with non-cache memory  
A system and method are provided for bypassing cache memory when reading data from system memory particularly when the primary memory could include memory types where the read operation mixes...
7155576 Pre-fetching and invalidating packet information in a cache memory  
A technique for managing a cache memory coupled to an intermediate node's processor. Packets acquired by the intermediate node that are destined for processing by the processor are tracked, without...
7152149 Disk array apparatus and control method for disk array apparatus  
A disk array apparatus that is capable of effecting saving and operation of data with a simple construction. When a host computer sets “write inhibit” or “read/write inhibit” for an LDEV...
7146454 Hiding refresh in 1T-SRAM architecture  
A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external...
7143243 Tag array access reduction in a cache memory  
A cache memory is disclosed with reduced tag array searches for sequential memory accesses. The cache memory has components such as at least one tag array, at least one data array associated with...
7143239 Cache structure and methodology  
A cache structure comprising a plurality of tag arrays and a plurality of data arrays, the tag arrays each configured to point to lines of data in multiple ones of the plurality of data arrays,...
7143245 System and method for read migratory optimization in a cache coherency protocol  
A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to...
7143240 System and method for providing a cost-adaptive cache  
A cost-adaptive cache including the ability to dynamically maximize performance in a caching system by preferentially caching data according to the cost of replacing data. The cost adaptive cache...
7139878 Method and apparatus for dynamic prefetch buffer configuration and replacement  
A memory controller and method thereof configures a prefetch buffer dynamically for interfacing between multiple bus masters of different burst support and multiple memories having different...
7136968 System and method for maintaining cache consistency in a wireless communication system  
An invalidation bit pattern (IBP) for maintaining transaction cache consistency in a wireless communication system is provided. The IBP comprises at least one bit corresponding to at least one...
7136969 Using the message fabric to maintain cache coherency of local caches of global memory  
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
7133973 Arithmetic processor  
An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the...
7130965 Apparatus and method for store address for store address prefetch and line locking  
Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at...
7127561 Coherency techniques for suspending execution of a thread until a specified memory access occurs  
Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having...
7127562 Ensuring orderly forward progress in granting snoop castout requests  
A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request...
7124254 Method and structure for monitoring pollution and prefetches due to speculative accesses  
A method and structure for equipping a cache with information to enable the processor to track and report whether a given speculative access causes prefetches and/or pollutions of the cache. Two...
7124236 Microprocessor including bank-pipelined cache with asynchronous data blocks  
A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which...
7117308 Hypertransport data path protocol  
A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus....
7114036 Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected  
A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a...
7111146 Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine  
A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host...
7107410 Exclusive status tags  
The disclosed embodiments relate to exclusive status tags. A multiprocessor computer system may include multiple processors and caches that may be managed by a directory or snooping. To optimize...
7107405 Writing cached data to system management memory  
In one embodiment of the present invention, a method includes storing system management mode data in a cache of a system during a system management mode; and preventing the system from leaving the...
7103720 Shader cache using a coherency protocol  
Methods and systems for caching graphics data using dedicated level one caches and a shared level two cache are described. Furthermore, each method includes a protocol for maintaining coherency...
7103736 System for repair of ROM programming errors or defects  
A system is disclosed for use of imperfect ROMs in embedded systems. The ROM or other memory accessible upon start-up of the system, includes a stored program which checks an external source to...
7096323 Computer system with processor cache that stores remote cache presence information  
A computer system with a processor cache that stores remote cache presence information. In one embodiment, a plurality of presence vectors are stored to indicate whether particular blocks of data...
Matches 151 - 200 out of 884 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >