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7376798 |
Memory management methods and systems that support cache consistency
Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an...
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7376799 |
System for reducing the latency of exclusive read requests in a symmetric multi-processing system
A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with...
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7373461 |
Speculative directory lookup for sharing classification
In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence...
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7373457 |
Cache coherence protocol for a multiple bus multiprocessor system
A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There...
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7370152 |
Memory controller with prefetching capability
A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of...
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7370154 |
Method and apparatus for maintaining coherence information in multi-cache systems
A method and apparatus for maintaining coherence information in multi-cache systems is described herein. In one embodiment, the apparatus includes an Ingrained Sharing Directory Cache (ISDC) to...
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7366847 |
Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag
A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter...
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7366845 |
Pushing of clean data to one or more processors in a system having a coherency protocol
Techniques for pushing data to multiple processors in a clean state.
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7366848 |
Reducing resource consumption by ineffective write operations in a shared memory system
In a shared memory system, ineffective write operations (“dead stores”) can be handled in a manner to reduce unnecessary consumption of resources. In a shared memory system, when a non-owning...
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7366846 |
Redirection of storage access requests
Provided are a method, system, and article of manufacture, wherein a controller receives a request from one of a plurality of hosts. The controller determines whether a primary storage control unit...
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7363435 |
System and method for coherence prediction
A coherence prediction mechanism includes a synchronization manager and a plurality of access predictors. The synchronization manager maintains one or more sequence entries, each sequence entry...
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7360031 |
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface...
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7356651 |
Data-aware cache state machine
A method and system directed to improve effectiveness and efficiency of cache and data management by differentiating data based on certain attributes associated with the data and reducing the...
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7353319 |
Method and apparatus for segregating shared and non-shared data in cache memory banks
In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or...
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7353341 |
System and method for canceling write back operation during simultaneous snoop push or snoop kill operation in write back caches
A cache write back operation, write back modified data to memory from cache data array to fix inconsistency between them can be cancelled by the results of a comparison of the progress between a...
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7350032 |
Cache coherency protocol including generic transient states
In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of...
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7350033 |
Methods and systems for providing validity logic
Systems and methods are disclosed for providing validity logic. The disclosed systems and methods may include receiving at least one data value, determining validity data corresponding to the...
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7350025 |
System and method for improved collection of software application profile data for performance optimization
The present invention is directed to a system and method for improved collection of application profile data for performance optimization. The invention provides a mechanism for storing usage bits...
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7346735 |
Virtualized load buffers
A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access...
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7337276 |
Method and apparatus for aging data in a cache
A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier...
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7334089 |
Methods and apparatus for providing cache state information
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a...
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7330934 |
Cache memory with reduced power and increased memory bandwidth
A digital processor with a cache that provides fast and low power operation. The cache contains a tag array and a data array. The tag array indicates whether a value is stored in the cache for a...
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7330937 |
Management of stack-based memory usage in a processor
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and...
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7328311 |
Memory controller controlling cashed DRAM
According to the semiconductor device and method of the present invention, because regular cache memories subjected to hit checks are distinguished from spare cache memories not subjected to hit...
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7325101 |
Techniques for reducing off-chip cache memory accesses
Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main...
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7321986 |
Configuring cache memory from a storage controller
Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first...
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7318126 |
Asynchronous symmetric multiprocessing
An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for...
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7318127 |
Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor
A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The...
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7318074 |
System and method for achieving deferred invalidation consistency
In a system having a plurality of caches, a method for maintaining cached objects includes storing an object in a plurality of caches. In response to a request to update the object, a future...
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7315920 |
Circuit and method for protecting vector tags in high performance microprocessors
The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a...
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7310709 |
Method and apparatus for primary cache tag error handling
A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache,...
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7308539 |
Concurrent read access and exclusive write access to data in shared memory architecture
Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of...
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7308536 |
System bus read data transfers with data ordering control bits
A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to...
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7305524 |
Snoop filter directory mechanism in coherency shared memory system
Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout...
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7302530 |
Method of updating cache state information where stores only read the cache state information upon entering the queue
The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering...
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7296120 |
Mechanism that provides efficient multi-word load atomicity
Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the...
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7296167 |
Combined system responses in a chip multiprocessor
In one embodiment, a node comprises, integrated onto a single integrated circuit chip (in some embodiments), a plurality of processor cores and a node controller coupled to the plurality of...
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7293196 |
Method, apparatus, and system for preserving cache data of redundant storage controllers
A method, apparatus, and system for preserving the cache data of redundant storage controllers, by copying the recorded data blocks and the associated cache tags in the primary cache memory of a...
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7290081 |
Apparatus and method for implementing a ROM patch using a lockable cache
A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first...
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7290093 |
Cache memory to support a processor's power mode of operation
A system, method, and apparatus for a cache memory to support a low power mode of operation.
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7284097 |
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going...
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7281092 |
System and method of managing cache hierarchies with adaptive mechanisms
A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a...
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7278013 |
Apparatus having a cache and a loop buffer
Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.
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7277992 |
Cache eviction technique for reducing cache eviction traffic
A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an...
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7269168 |
Host bus adaptor-based virtualization switch
Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be...
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7266647 |
List based method and apparatus for selective and rapid cache flushes
An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache...
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7266642 |
Cache residence prediction
The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the...
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7263586 |
Cache coherency for multiple independent cache of a domain
Distinguishing between snoops initiated internally with respect to a processing unit and snoops initiated externally with respect to a processing unit allows maintenance of cache coherency for a...
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7243191 |
Compressing data in a cache memory
In one embodiment, the present invention includes a cache memory having a plurality of cache lines to store data, in which at least some of the cache lines are adapted to store data in a compressed...
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7240165 |
System and method for providing parallel data requests
A multi-processor system includes a requesting node that provides a first request for data to a home node. The requesting node being operative to provide a second request for the data to at least...
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