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7496715 |
Programmable cache management system and method
A memory control system and method is disclosed. The system includes cache tag logic and an optional cache coupled to a main memory. If available, the cache retains a subset of the data stored...
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7493453 |
System, method and storage medium for prefetching via memory block tags
A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory...
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7493452 |
Method to efficiently prefetch and batch compiler-assisted software cache accesses
A method to efficiently pre-fetch and batch compiler-assisted software cache accesses is provided. The method reduces the overhead associated with software cache directory accesses. With the...
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7487295 |
Memory control device and move-in buffer control method
A central processor requests for reference to data stored in a main storage for each of a plurality of threads. A thread identification information obtaining unit obtains thread identification...
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7484042 |
Data processing system and method for predictively selecting a scope of a prefetch operation
A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains,...
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7484044 |
Method and apparatus for joint cache coherency states in multi-interface caches
A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache...
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7484054 |
System and method for performing storage operations in a computer network
Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection...
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7483930 |
Method and apparatus for maintaining an object-based write barrier to facilitate garbage-collection operations
One embodiment of the present invention provides a system that facilitates identifying roots for a garbage-collection operation in a computer system that supports an object-addressed memory...
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7480771 |
Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged
We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated,...
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7480772 |
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory...
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7480770 |
Semi-blocking deterministic directory coherence
In one embodiment, a node for a multi-node computer system comprises a coherence directory and a coherence controller. The coherence directory comprises a plurality of entries, wherein each entry...
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7478202 |
Using the message fabric to maintain cache coherency of local caches of global memory
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
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7478203 |
Technique for eliminating dead stores in a processor
A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the...
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7478218 |
Adaptive cache sizing based on monitoring of regenerated and replaced cache entries
A runtime code manipulation system is provided that supports code transformations on a program while it executes. The runtime code manipulation system uses code caching technology to provide...
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7475196 |
Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains
A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor...
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7475194 |
Apparatus for aging data in a cache
A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier...
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7472231 |
Storage area network data cache
A cache connected to the virtualization engine in the center of a storage area network. The invention caches data in a virtual cache, without requiring translation to the physical location. The...
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7469318 |
System bus structure for large L2 cache array topology with different latency domains
A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock...
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7467280 |
Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring...
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7464227 |
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an...
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7461209 |
Transient cache storage with discard function for disposable data
A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache...
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7454578 |
Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory
A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the...
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7444476 |
System and method for code and data security in a semiconductor device
A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data...
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7434007 |
Management of cache memories in a data processing apparatus
The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking...
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7428617 |
Cache memory and method to maintain cache-coherence between cache memory units
A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a...
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7426626 |
TLB lock indicator
A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The...
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7426627 |
Selective address translation for a resource such as a hardware device
A computing system has a resource for providing resource services, where each resource service is accessed by way of a system address (SA). A device requests the resource services of the resource...
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7421624 |
Data recovery apparatus and method used for flash memory
A data recovery apparatus and method used for a flash memory, which can recover data damaged or lost when power supplied to the flash memory is cut off while data operations are being consecutively...
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7418558 |
Information processing system, system control apparatus, and system control method
A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control...
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7418526 |
Memory hub and method for providing memory sequencing hints
A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of...
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7415577 |
Method and apparatus to write back data
Briefly, in accordance with an embodiment of the invention, a method and apparatus to write back data is provided. The method may include setting a status corresponding to a block of data in...
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7412567 |
Value-based memory coherence support
In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to...
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7412569 |
System and method to track changes in memory
Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary...
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7401185 |
Buffered indexing to manage hierarchical tables
Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new...
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7398377 |
Apparatus and method for target address replacement in speculative branch target address cache
An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid...
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7395378 |
System and method for updating a copy-on-write snapshot based on a dirty region log
Various methods and systems for updating a copy-on-write snapshot based on a dirty region log are disclosed. For example, a method involves maintaining a dirty region log and updating a...
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7395380 |
Selective snooping by snoop masters to locate updated data
A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less...
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7395373 |
Set-associative cache using cache line decay counts and set overflow
Embodiments of a method for reducing conflict misses in a set-associative cache by mapping each memory address to a primary set and at least one overflow set are described. If a conflict miss...
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7395379 |
Methods and apparatus for responding to a request cluster
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors...
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7388588 |
Programmable graphics processing engine
A fully programmable graphics processing engine is provided. The graphics processing engine includes three independent, programmable processors that run independent sets of instructions from...
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7389388 |
Data processing system and method for efficient communication utilizing an in coherency state
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory,...
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7389389 |
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a...
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7389383 |
Selectively unmarking load-marked cache lines during transactional program execution
One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are...
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7386678 |
Efficient system bootstrap loading
An efficient system for bootstrap loading scans cache lines into a cache store queue during a scan phase, and then transmits the cache lines from the cache store queue to a cache memory array...
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7383390 |
Resource-limited directories with fine-grained eviction
A system including a memory, a first processor operatively connected to a first cache, a second processor operatively connected to a second cache, a directory implemented in hardware operatively...
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7380070 |
Organization of dirty bits for a write-back cache
A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit or a miss into the cache system has...
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7380098 |
Method and system for caching attribute data for matching attributes with physical addresses
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
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7376796 |
Lightweight coherency control protocol for clustered storage system
A lightweight coherency control protocol ensures consistency of data containers, such as a file, and associated data buffers stored on one or more volumes served by a plurality of nodes, e.g.,...
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7376797 |
Cache memory system and method using reference bits
A cache memory system includes a cache memory having a plurality of entries associated with a plurality of information storage units. Each of the information storage units is configured to store...
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7376800 |
Speculative multiaddress atomicity
A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively...
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