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6085292 Apparatus and method for providing non-blocking pipelined cache  
A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A...
6078991 Method and system for speculatively requesting system data bus for sourcing cache memory data within a multiprocessor data-processing system  
A method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the...
6078997 Directory-based coherency system for maintaining coherency in a dual-ported memory system  
Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are "Owned" and "Unowned." The state of the bit is used...
6073217 Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor  
A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction...
6073211 Method and system for memory updates within a multiprocessor data processing system  
An apparatus is disclosed which supports memory updates within a data processing system including a number of processors. The apparatus includes a memory hierarchy including one or more upper...
6070231 Method and apparatus for processing memory requests that require coherency transactions  
A method for processing memory requests and a memory controller that implements the method are disclosed. The method includes the steps of (a) receiving a first memory request from a first bus, (b)...
6070233 Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache  
A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status...
6061765 Independent victim data buffer and probe buffer release control utilzing control flag  
In accordance with the present invention, a method and apparatus is provided for storing victim data evicted from a cache and for satisfying pending requests or probe messages that target victim...
6052700 Calendar clock caching in a multiprocessor data processing system  
Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically...
6049851 Method and apparatus for checking cache coherency in a computer architecture  
A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a...
6044441 Method and apparatus for encoding valid and invalid states in a cache with an invalid pattern  
A cache controller unit includes an address comparator unit for comparing an address to be accessed in memory with a tag address. An invalid pattern comparator is coupled to the address comparator....
6038645 Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache  
A microprocessor (10) comprising a central processor unit core (12) operable to write information during a write cycle and a cache circuit (18) coupled to the central processor unit core and...
6038644 Multiprocessor system with partial broadcast capability of a cache coherent processing request  
Information indicative of whether each processor unit caches data which belongs to each of the plural areas of the main memory larger than a cache line is stored in the multicast table. The...
6035376 System and method for changing the states of directory-based caches and memories from read/write to read-only  
A system for converting between the states of fresh and owned in a multi-processor computer system comprises a memory line with a structure including a first field for storing a memory state, a...
6032229 Semiconductor memory device and information processor using the same  
An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a...
6021468 Cache coherency protocol with efficient write-through aliasing  
A method of maintaining cache coherency in a multi-processor computer system, which avoids unnecessary writing of values to lower level caches in response to write-through store operations. When a...
6021481 Effective-to-real address cache managing apparatus and method  
An effective-to-real address translation cache management apparatus and method utilizes an effective-to-real address translation cache segment register latch having a bit corresponding to each of...
6018792 Apparatus for performing a low latency memory read with concurrent snoop  
A computer system has a system memory, cache memory, system controller that process memory transactions. The system controller transmits a memory request to the system memory without waiting for...
6018794 Data processing apparatus and method for generating timing signals for a self-timed circuit  
A self-timed data processing circuit and method of operation of such a circuit are disclosed. The circuit comprises a plurality of components, such as memory cells, arranged to generate...
6018791 Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states  
A multi-processor computer system with clustered processing units uses a cache coherency protocol having a "recent" coherency state to indicate that a particular cache block containing a valid copy...
6014728 Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations  
A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to...
6000017 Hybrid tag architecture for a cache memory  
A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache...
5996050 Cache coherency detection in a bus bridge verification system  
A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address...
5996048 Inclusion vector architecture for a level two cache  
A cache architecture with a first level cache and a second level cache, with the second level cache lines including an inclusion vector which indicates which portion of that line are stored in the...
5995420 Integrated XNOR flip-flop for cache tag comparison  
An integrated XNOR flip-flop is provided which is faster than conventional XNOR flip-flop combinations. The integrated XNOR flip-flop is faster and uses less area than conventional XNOR flip-flop...
5983343 Data processing system having an apparatus for de-serialized status register operation and method therefor  
An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all...
5978886 Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache  
An apparatus and method for duplicating tag addresses to maintain addresses of central processing unit (CPU) data stored in write buffers external to a cache are disclosed. Advance notification of...
5974511 Cache subsystem with pseudo-packet switch  
A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus...
5974438 Scoreboard for cached multi-thread processes  
A computer system comprising at least one processor and associated cache memory, and a plurality of registers to keep track of the number of cache memory lines associated with each process thread...
5974508 Cache memory system and method for automatically locking cache entries to prevent selected memory items from being replaced  
A cache memory system has a plurality of cache entries for storing memory items staged from a memory. The cache memory system locks entries so that memory items stored therein are prevented from...
5963978 High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators  
A high-level (L2) cache and a efficient method for writing directory entries into an array of directory entries are disclosed. The high-level (L2) cache operates differently depending upon whether...
5958068 Cache array defect functional bypassing using repair mask  
A method of bypassing defects in a cache used by a processor of a computer system. A repair mask has an array of bit fields corresponding to cache lines in the cache, and when a particular cache...
5958019 Multiprocessing system configured to perform synchronization operations  
When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency...
5946716 Sectored virtual memory management system and translation look-aside buffer (TLB) for the same  
A memory management system is described which divides each virtual page into two or more sectors. Each of these sectors can then be individually loaded into memory in order to reduce bandwidth...
5943685 Method of shared intervention via a single data provider among shared caches for SMP bus  
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the...
5943684 Method and system of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system  
A method and system of providing a cache-coherency protocol for maintaining cache coherency within a multi-processor data-processing system is disclosed. In accordance with the method and system of...
5940860 Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains  
An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common...
5940864 Shared memory-access priorization method for multiprocessors using caches and snoop responses  
A method of reducing memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. When a requesting processing unit issues a message indicating that it...
5940856 Cache intervention from only one of many cache lines sharing an unmodified value  
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at...
5933849 Scalable distributed caching system and method  
A scalable distributed caching system on a network receives a request for a data object from a user. The caching system carries out a locator function that locates a directory cache for the object....
5933844 Write through virtual cache memory, alias addressing, and cache flushes  
In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are alias address to each other, a cache...
5926830 Data processing system and method for maintaining coherency between high and low level caches using inclusive states  
A data processing system and method for maintaining coherency between a high-level (L2) cache and a low-level (L1) cache are disclosed. The L2 (high-level) cache operates in a first mode of...
5923855 Multi-processor system and method for synchronizing among processors with cache memory having reset state, invalid state, and valid state  
In a multi-processor system including a plurality of processing units each having a cache memory, the processing units each include a synchronization counter for indicating a present...
5920891 Architecture and method for controlling a cache memory  
A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory...
5920890 Distributed tag cache memory system and method for storing data in the same  
A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU...
5913226 Snoop cache memory control system and method  
To implement a system minimizing access to the shared memory, the previous owner number storage module contains the number of a cache memory or the shared memory which was the previous owner of...
5913224 Programmable cache including a non-lockable data way and a lockable data way configured to lock real-time data  
A computer system is disclosed which provides for execution of real-time code from cache memory. A cache management unit provides the real-time code to the cache memory from system memory upon a...
5913228 Method and apparatus for caching discontiguous address spaces with short cache tags  
A method and apparatus for determining whether an address corresponds to a cacheable memory location within a discontiguously-arranged cacheable memory space. In one embodiment, the present...
5909695 Maximal concurrent lookup cache for computing systems having a multi-threaded environment  
A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry being identified by an entry number....
5909696 Method and apparatus for caching system management mode information with other information  
A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data...
Matches 601 - 650 out of 884 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >