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6546462 |
CLFLUSH micro-architectural implementation method and system
A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether...
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6542965 |
Cache line replacement using cable status to bias way selection
A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice...
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6526480 |
Cache apparatus and control method allowing speculative processing of data
The invention relates to cache apparatuses and a control method for managing cache memories in a multiprocessor system. A cache controller holds data which has to be invalidated for a cache...
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6523095 |
Method and data processing system for using quick decode instructions
A cache line of a cache ( 230 ) contains a modifiable instruction. The modifiable instruction is decoded by a central processor unit ( 210 ) (CPU) which performs the function associated with the...
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6516384 |
Method and apparatus to perform a round robin and locking cache replacement scheme
A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers are daisy chained together with each...
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6502168 |
Cache having virtual cache controller queues
According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries...
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6496905 |
Write buffer with burst capability
Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer...
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6493797 |
Multi-tag system and method for cache read/write
A method and device are provided for reading data from a trace cache in a manner that reduces the time and power consumed by such an operation. A mini-tag is provided for comparing to a requested...
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6493802 |
Method and apparatus for performing speculative memory fills into a microprocessor
According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which...
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6490657 |
Cache flush apparatus and computer system having the same
Addresses of all of dirty blocks of a cache memory are, by an update address registering section, stored in one of plural regions of an update address memory. When a certain cache block is brought...
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6487641 |
Dynamic caches with miss tables
A middle-tier Web server with a queryable cache that contains items from one or more data sources. Items are included in the cache on the basis of the probability of future hits on the items. When...
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6484242 |
Cache access control system
A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L 1 cache...
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6470437 |
Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design
In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to...
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6467031 |
Method and apparatus for reducing processor bus loading
A method and apparatus to reduce processor bus loading is provided. A method of reducing processor bus loading in a system having a processor with a first processor bus granularity, a memory...
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6467024 |
Accessing data volumes from data storage libraries in a redundant copy synchronization token tracking system
Disclosed are a data storage library subsystem, and a method which may be implemented by a computer program product, for increasing the accessing performance of data volumes from libraries in a...
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6457120 |
Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions
A superscalar processor and method are disclosed for improving the accuracy of predictions of a destination of a branch instruction utilizing a cache. The cache is established including multiple...
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6449695 |
Data cache using plural lists to indicate sequence of data storage
A cache system controls the insertion and deletion of data items using a plurality of utilization lists. When a data item is stored within the data cache, a corresponding data pointer, or other...
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6449709 |
Fast stack save and restore system and method
A processor includes a stack that operates as a circular stack and appears to the address space in the memory of the processor as a single point address location. The stack supports read and write...
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6446167 |
Cache prefetching of L2 and L3
A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory....
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6442654 |
Operating system support for in-server caching of documents
A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache....
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6442653 |
Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data
A data processing system includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit...
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6438661 |
Method, system, and program for managing meta data in a storage system and rebuilding lost meta data in cache
Disclosed is a method, system, and article of manufacture for processing modified meta data for data recovery operations. The meta data provides information on user data maintained in a storage...
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6438651 |
Method, system, and program for managing requests to a cache using flags to queue and dequeue data in a buffer
Provided is a system, method, and program for managing read and write requests to a cache to process enqueue and dequeue operations for a queue. Upon receiving a data access request to a data block...
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6438650 |
Method and apparatus for processing cache misses
A system for processing caches misses includes a request miss buffer, secondary miss logic, and a request identifier buffer. When a request misses in a cache, information characterizing the request...
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6427207 |
Result forwarding cache
An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing—that are not...
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6425060 |
Circuit arrangement and method with state-based transaction scheduling
A data processing system, circuit arrangement, and method rely on state information to prioritize certain transactions relative to other transactions when scheduling transactions in a data...
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6421764 |
Method and apparatus for efficient clearing of memory
A method and apparatus for clearing memory, or portions thereof in a fast and efficient manner begins by representing a group of memory locations by a representative value. When a particular group...
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6415358 |
Cache coherency protocol having an imprecise hovering (H) state for instructions and data
A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of processors that are each associated with a respective...
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6412051 |
System and method for controlling a memory array in an information handling system
A system and method for allowing operation of a storage array after a failure within a set of an n-way set associative cache includes determining that there is a failure in a bit line in the...
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6408365 |
Multiprocessor system having means for arbitrating between memory access request and coherency maintenance control
A multiprocessor system has a controller for arbitrating a memory access request and a coherency maintenance control process. A coherency maintenance controller for maintaining coherency of data...
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6408361 |
Autonomous way specific tag update
The present invention provides a method and apparatus for allowing autonomous, way specific tag updates. More specifically, the invention provides way specific tag and status updates while...
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6405287 |
Cache line replacement using cache status to bias way selection
A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice...
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6405289 |
Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response
A method of maintaining cache coherency, by designating one cache that owns a line as a highest point of coherency (HPC) for a particular memory block, and sending a snoop response from the cache...
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6405322 |
System and method for recovery from address errors
A device and method for recovery from address errors is described. When an address error is detected on a local channel, such as a local bus, the coherency states of one or more lines of cache...
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6401172 |
Recycle mechanism for a processing agent
A method of processing a data request in a processing agent. The method comprises posting the data request internally within the agent and, if the data request implicates data associated with a...
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6397304 |
Method and apparatus for improving system performance in multiprocessor systems
A method and apparatus to retrieve data for a multiprocessor system is described. A request for data is received at a first processor from a bus. A cache is searched for the data, with the data...
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6397305 |
Method and apparatus for controlling shared memory access
A method and apparatus for controlling memory access in a system where at least a first and a second processor each share a common memory. The first processor has a write buffer, in which it stores...
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6393553 |
Acknowledgement mechanism for just-in-time delivery of load data
A system which permits dynamic verification of the availability of a desired time at which to load a data requested by a load instruction. The system comprises (i) means for appending a time...
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6389517 |
Maintaining snoop traffic throughput in presence of an atomic operation a first port for a first queue tracks cache requests and a second port for a second queue snoops that have yet to be filtered
Apparatus and method to permit snoop filtering to occur while an atomic operation is pending. The snoop filtering apparatus includes first and second request queues and a cache. The first request...
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6385702 |
High performance multiprocessor system with exclusive-deallocate cache state
A cache coherency protocol uses a “Exclusive-Deallocate” (E D ) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form...
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6385695 |
Method and system for maintaining allocation information on data castout from an upper level cache
A method and system for maintaining allocation information on data castout from an upper level cache provides a cache control with the ability to select victims based on whether a cache entry is...
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6378048 |
“SLIME” cache coherency system for agents with multi-layer caches
A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state,...
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6374333 |
Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention
A novel cache coherency protocol provides a modified-unsolicited (M U ) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system...
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6374329 |
High-availability super server
A high-availability parallel processing server has multiple processors that are grouped into processor clusters and a plurality of memory segments. Each cluster may have up to four processors, and...
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6360301 |
Coherency protocol for computer cache
A lower level cache detects when a line of memory has been evicted from a higher level cache. The cache coherency protocol for the lower level cache places the line into a special state. If a line...
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6356982 |
Dynamic mechanism to upgrade o state memory-consistent cache lines
A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to...
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6353874 |
Method and apparatus for controlling and caching memory read operations in a processing system
A method and apparatus for controlling and caching memory read operations is presented. A memory structure is used to store data for read operations in a manner that allows the data to be reused in...
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6353877 |
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write
A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge...
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6351790 |
Cache coherency mechanism
A cache coherency mechanism for a computer system having a plurality of processors, each for executing a sequence of instructions, at least one of the processors having a cache memory associated...
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6351791 |
Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responses
A data processing system, circuit arrangement, integrated circuit device, program product, and method improve system response by disregarding extraneous retry signals during the generation of a...
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