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7624236 Predictive early write-back of owned cache blocks in a shared memory computer system  
A method for predicting early write back of owned cache blocks in a shared memory computer system. This invention enables the system to predict which written blocks may be more likely to be...
7606978 Multi-node computer system implementing global access state dependent transactions  
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to...
7581042 I/O hub resident cache line monitor and device register update  
The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a...
7555610 Cache memory and control method thereof  
The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will...
7536428 Concurrent read and write access to a linked list where write process updates the linked list by swapping updated version of the linked list with internal list  
A method and computing device for providing concurrent read and write access to a linked list of elements is presented. A linked list is provided wherein read access by a reader process and write...
7523268 Reducing number of rejected snoop requests by extending time to respond to snoop request  
A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if...
7502903 Method and apparatus for managing data storage systems  
A method is provided for a data storage system to move data from a source logical disk (LD) region to a target LD region while the data storage system remains online to a host. The method includes...
7484044 Method and apparatus for joint cache coherency states in multi-interface caches  
A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache...
7484046 Reducing number of rejected snoop requests by extending time to respond to snoop request  
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address,...
7478202 Using the message fabric to maintain cache coherency of local caches of global memory  
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
7475191 Processor, data processing system and method for synchronizing access to data in shared memory  
A processing unit for a multiprocessor data processing system includes a processor core and a lower level cache including a reservation logic that records reservations of the processor core. The...
7472229 Bus controller initiated write-through mechanism  
A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid,...
7472230 Preemptive write back controller  
A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The...
7447812 Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files  
Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According...
7376789 Wide-port context cache apparatus, systems, and methods  
Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of...
7376799 System for reducing the latency of exclusive read requests in a symmetric multi-processing system  
A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with...
7360031 Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces  
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface...
7356651 Data-aware cache state machine  
A method and system directed to improve effectiveness and efficiency of cache and data management by differentiating data based on certain attributes associated with the data and reducing the...
7340563 Data transmission device having the shape of a standard 3.5″ disk  
A data transmission device includes a memory cache table ( 4 ) composed of a DRAM memory, a standard 2.5″ hard disk ( 5 ), a control CPU ( 7 ), a FPGA ( 6 ) (or ASIC), a disk interface ( 3 ) and...
7263580 Cache flush based on checkpoint timer  
A data processing system is used which is provided with a computer for executing a program, and a storage unit having a cache memory for storing data transmitted as a result of execution of the...
7254686 Switching between mirrored and non-mirrored volumes  
Provided are a method, system, and article of manufacture, wherein a request is received for switching a logical volume from one state to another state, wherein the logical volume is in a mirrored...
7237069 Arrangement and method for update of configuration cache data  
An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory ( 110 ) is updated using two-phase ( 220, 250 ) commit technique. This provides...
7234028 Power/performance optimized cache using memory write prevention through write snarfing  
A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or...
7233880 Adaptive cache algorithm for temperature sensitive memory  
A temperature sensitive memory, such as a ferroelectric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be...
7231497 Merging write-back and write-through cache policies  
In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of...
7219197 Cache memory, processor and cache control method  
A cache memory, comprising: a data storage capable of storing data which requires consistency of data with a main memory; and a storage controller which controls to store data which does not...
7216202 Method and apparatus for supporting one or more servers on a single semiconductor chip  
One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to...
7194587 Localized cache block flush instruction  
A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending...
7185029 Method and apparatus for maintaining, and updating in-memory copies of the first and second pointers to reference the new versions of the first and second control structures that indicate available and allocated portions of usable space in the data file  
Method and apparatus for expanding usable space for an application data file. A control file is maintained with control structures that indicate available and allocated portions of usable space in...
7177987 System and method for responses between different cache coherency protocols  
Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency...
7162625 System and method for testing memory during boot operation idle periods  
The present invention discloses an information handling system that reduces POST time in a boot operation. The information handling system includes a processor, a memory and a BIOS unit. The BIOS...
7159079 Multiprocessor system  
A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 ...
7136969 Using the message fabric to maintain cache coherency of local caches of global memory  
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
7120752 Multi-processor computer system with cache-flushing system using memory recall  
A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of...
7103722 Cache configuration for compressed memory systems  
A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines...
7082500 Optimized high bandwidth cache coherence mechanism  
A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A...
7076613 Cache line pre-load and pre-own based on cache coherence speculation  
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor...
7076614 System and method for optimizing bus bandwidth utilization by grouping cache write-backs  
A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by...
7039908 Unification-based points-to-analysis using multilevel typing  
Location types in unification-based, flow-insensitive “points-to” analyses represent three kinds of sets of abstract memory locations in a three-level subtyping system. The data constructor for...
7003631 System having address-based intranode coherency and data-based internode coherency  
A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is...
6996683 Cache coherency in a multi-processor system  
A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also...
6993631 L2 cache maintaining local ownership of remote coherency blocks  
A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first...
6988170 Scalable architecture based on single-chip multiprocessing  
A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory...
6983348 Methods and apparatus for cache intervention  
Methods and Apparatus for cache-to-cache transfers upon snooping a cache interconnect to detect a memory read request associated with a cache memory block cached in a first cache and a second...
6981097 Token based cache-coherence protocol  
A cache coherence mechanism for a shared memory computer architecture employs tokens to designate a particular node's rights with respect to writing or reading a block of shared memory. The token...
6973544 Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system  
A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a...
6965973 Remote line directory which covers subset of shareable CC-NUMA memory space  
A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total...
6941423 Non-volatile mass storage cache coherency apparatus  
Apparatus and methods relating to a cache coherency administrator. The cache coherency administrator can include a display to indicate a cache coherency status of a non-volatile cache.
6938129 Distributed memory module cache  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6938127 Reconfiguring memory to reduce boot time  
A processor-based system includes a system firmware program that is transferred to a designated region of a memory in response to an initialization (e.g., a boot sequence). When initialized, for...
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