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8447924 |
Computer system having an expansion device for virtualizing a migration source wherein the operation mode of the computer is set to a cache through or write after mode
A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration...
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8443134 |
Apparatus, system, and method for graceful cache device degradation
Apparatuses, systems, and methods are disclosed for implementing a cache policy. A method may include determining a risk of data loss on a cache device. The cache device may comprise a non-volatile...
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8423721 |
Cache coherency protocol in a data processing system
A method includes detecting a bus transaction on a system interconnect of a data processing system having at least two masters; determining whether the bus transaction is one of a first type of bus...
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8412911 |
System and method to invalidate obsolete address translations
A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in...
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8402225 |
Method for performing cache coherency in a computer system
In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique...
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8392664 |
Network on chip
A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through...
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8386664 |
Reducing runtime coherency checking with global data flow analysis
Reducing runtime coherency checking using global data flow analysis is provided. A determination is made as to whether a call is for at least one of a DMA get operation or a DMA put operation in...
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8375172 |
Preventing fast read before write in static random access memory arrays
A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines...
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8321701 |
Adaptive flushing of storage data
Methods and a processing device are provided for monitoring a level of power in a power supply of a processing device and changing a data flushing policy, with respect to data to be written to a...
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8307270 |
Advanced memory device having improved performance, reduced power and increased reliability
An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error...
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8301844 |
Consistency evaluation of program execution across at least one memory barrier
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier....
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8266386 |
Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocols
A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a...
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8250304 |
Cache memory device and system with set and group limited priority and casting management of I/O type data injection
A memory device comprising a cache memory with a predetermined amount of cache sets, each cache set comprising a predetermined amount of cache lines. Each cache line is operable to indicate a cache...
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8219745 |
Memory controller to utilize DRAM write buffers
A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM...
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8161248 |
Simplifying and speeding the management of intra-node cache coherence
A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm...
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8122197 |
Managing coherence via put/get windows
A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm...
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8117400 |
System and method for fetching an information unit
A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from...
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8108618 |
Method and apparatus for maintaining memory data integrity in an information handling system using cache coherency protocols
An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache...
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8090907 |
Method for migration of synchronous remote copy service to a virtualization appliance
A method, system, computer program product, and computer program storage device for receiving and processing I/O requests from a host device and providing data consistency in both a primary site...
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8074026 |
Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
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8051246 |
Method and apparatus for utilizing a semiconductor memory of a node as a disk cache
A method and apparatus for utilizing a semiconductor memory of a node as disk cache is described. In one embodiment, a method of utilizing a semiconductor memory of a second server for a first...
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8015351 |
Computer system having an expansion device for virtualizing a migration source logical unit
A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration...
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7937535 |
Managing cache coherency in a data processing apparatus
Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access...
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7877550 |
Bus controller initiated write-through mechanism with hardware automatically generated clean command
A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid,...
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7870343 |
Managing coherence via put/get windows
A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm...
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7861052 |
Computer system having an expansion device for virtualizing a migration source logical unit
A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration...
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7818511 |
Reducing number of rejected snoop requests by extending time to respond to snoop request
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of ...
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7814292 |
Memory attribute speculation
A technique to speculatively assign a memory attribute. More specifically, embodiments of the invention include an architecture to assign and issue a speculative memory attribute based on a...
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7802058 |
Method for performing cache coherency in a computer system
In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Cache coherency is performed on appropriate caches in the...
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7797495 |
Distributed directory cache
A system and method for a distributed directory cache in a computing system. A system comprises a plurality of nodes including at least a source node, home node, and one or more target nodes. The...
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7774554 |
System and method for intelligent software-controlled cache injection
A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a...
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7730257 |
Method and computer program product to increase I/O write performance in a redundant array
A method and related computer program product for achieving high performance I/O write rates in a redundant array using a fully recoverable communication queue stored in NVRAM on a RAID controller...
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7725661 |
Data-aware cache state machine
Management of a Cache is provided by differentiating data base on attributes associated with the data and reducing storage bottlenecks. The Cache differentiates and manages data using a state...
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7711721 |
Apparatus, system, and method for suspending a request during file server serialization reinitialization
An apparatus, system, and method are disclosed for suspending a data access request during serialization reinitialization of a file server. The apparatus includes a request recognition module, an...
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7707460 |
Method, apparatus and program storage device for protecting data writes in a data storage device
A method, apparatus and program storage device for protecting data write operations against write failures in a data storage device is provided. The data storage device includes a storage medium, a...
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7698506 |
Partial tag offloading for storage server victim cache
A technique for partially offloading, from a main cache in a storage server, the storage of cache tags for data blocks in a victim cache of the storage server, is described. The technique includes...
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7624236 |
Predictive early write-back of owned cache blocks in a shared memory computer system
A method for predicting early write back of owned cache blocks in a shared memory computer system. This invention enables the system to predict which written blocks may be more likely to be...
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7606978 |
Multi-node computer system implementing global access state dependent transactions
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to...
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7581042 |
I/O hub resident cache line monitor and device register update
The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a...
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7555610 |
Cache memory and control method thereof
The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be...
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7536428 |
Concurrent read and write access to a linked list where write process updates the linked list by swapping updated version of the linked list with internal list
A method and computing device for providing concurrent read and write access to a linked list of elements is presented. A linked list is provided wherein read access by a reader process and write...
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7523268 |
Reducing number of rejected snoop requests by extending time to respond to snoop request
A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if...
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7502903 |
Method and apparatus for managing data storage systems
A method is provided for a data storage system to move data from a source logical disk (LD) region to a target LD region while the data storage system remains online to a host. The method includes...
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7484046 |
Reducing number of rejected snoop requests by extending time to respond to snoop request
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of ...
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7484044 |
Method and apparatus for joint cache coherency states in multi-interface caches
A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache...
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7478202 |
Using the message fabric to maintain cache coherency of local caches of global memory
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
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7475191 |
Processor, data processing system and method for synchronizing access to data in shared memory
A processing unit for a multiprocessor data processing system includes a processor core and a lower level cache including a reservation logic that records reservations of the processor core. The...
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7472229 |
Bus controller initiated write-through mechanism
A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid,...
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7472230 |
Preemptive write back controller
A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The...
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7447812 |
Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files
Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According...
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