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9043559 Block memory engine with memory corruption detection  
Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory...
9043530 Data storage within hybrid storage aggregate  
Among other things, one or more techniques and/or systems are provided for storing data within a hybrid storage aggregate comprising a lower-latency storage tier and a higher-latency storage tier....
9043554 Cache policies for uncacheable memory requests  
Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the...
9037791 Tiered caching and migration in differing granularities  
For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and managed tiered levels...
9032151 Method and system for ensuring reliability of cache data and metadata subsequent to a reboot  
To ensure that the contents of a non-volatile memory device cache may be relied upon as accurately reflecting data stored on disk storage, it may be determined whether the cache contents and/or...
9032160 Continuous data replication  
In a first embodiment, a method and computer program product for use in a storage system comprising quiescing IO commands the sites of an ACTIVE/ACTIVE storage system, the active/active storage...
9026742 System and method for processing potentially self-inconsistent memory transactions  
A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second...
9026736 System and method for maintaining cache coherency  
Described herein is a system and method for maintaining cache coherency. The system and method may maintain coherency for a cache memory that is coupled to a plurality of primary storage devices....
9026743 Flexible replication with skewed mapping in multi-core chips  
For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip....
9021212 Semiconductor memory system having a snapshot function  
In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical...
9021209 Cache flush based on idle prediction and probe activity level  
A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above...
9021211 Epoch-based recovery for coherent attached processor proxy  
A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP...
9015416 Efficient cache validation and content retrieval in a content delivery network  
Some embodiments provide systems and methods for validating cached content based on changes in the content instead of an expiration interval. One method involves caching content and a first...
9015424 Write transaction management within a memory interconnect  
A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may...
9015719 Scheduling of tasks to be performed by a non-coherent device  
A method for scheduling tasks to be processed by one of a plurality of non-coherent processing devices, at least two of the devices being heterogeneous devices and at least some of said tasks...
9009416 System and method for managing cache system content directories  
A method, computer program product, and computing system for reclassifying a first assigned cache portion associated with a first machine as a public cache portion associated with the first...
9009411 Flexible control mechanism for store gathering in a write buffer  
A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering...
9009364 Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed  
A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the...
9009214 Management of process-to-process inter-cluster communication requests  
A mechanism is provided for managing a process-to-process inter-cluster communication request. A call from a first application is received in a first operating system in a first data processing...
9003130 Multi-core processing device with invalidation cache tags and methods  
A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated...
9003162 Structuring storage based on latch-free B-trees  
A request to modify an object in storage that is associated with one or more computing devices may be obtained, the storage organized based on a latch-free B-tree structure. A storage address of...
8996829 Consistency without ordering dependency  
Aspects of the subject matter described herein relate to maintaining consistency in a storage system. In aspects, one or more objects may be updated in the context of a transaction. In conjunction...
8996820 Multi-core processor system, cache coherency control method, and computer product  
A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by...
8996812 Write-back coherency data cache for resolving read/write conflicts  
A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is...
8990501 Multiple cluster processor  
A multiple processor system is disclosed. The processor system includes a first cluster including a first plurality of processors is associated with a first cluster cache, a second cluster...
8990510 Read-copy update system and method  
A method, system and computer program product for managing requests for deferred updates to shared data elements while minimizing grace period detection overhead associated with determining...
8990511 Multiprocessor, cache synchronization control method and program therefor  
There is provided a cache synchronization control method by which contents of a plurality of caches can be synchronized without a programmer explicitly setting a synchronization point, and the...
8984218 Drive indicating mechanism for removable media  
A system (and associated method) comprises a storage drive and a central processing unit (“CPU”). The storage drive is adapted to accommodate a removable storage medium. The CPU is configured to...
8984233 Error detection for files  
Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile...
8977820 Handling of hard errors in a cache of a data processing apparatus  
A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. Cache location avoid storage is provided having at least one...
8972667 Exchanging data between memory controllers  
A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled...
8972663 Broadcast cache coherence on partially-ordered network  
A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave...
8965995 Wireless storage management system  
A wireless storage management system adapted for being used in an electronic product for wirelessly communicating with a plurality of wireless storage devices includes an identity module assigning...
8966178 Populating a first stride of tracks from a first cache to write to a second stride in a second cache  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
8966180 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8966461 Vector width-aware synchronization-elision for vector processors  
A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent...
8966187 Flexible replication with skewed mapping in multi-core chips  
For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip....
8959279 Populating a first stride of tracks from a first cache to write to a second stride in a second cache  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
8959289 Data cache block deallocate requests  
A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is...
8959290 Methods and apparatus for reusing snoop responses and data phase results in a cache controller  
Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller,...
8954672 System and method for cache organization in row-based memories  
The present disclosure relates to a method and system for mapping cache lines to a row-based cache. In particular, a method includes, in response to a plurality of memory access requests each...
8954682 Computer system management apparatus and management method  
The present invention measures an actual utilization frequency of data and controls a location of this data in a storage apparatus in a case where a host computer makes joint use of a storage...
8954674 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8954474 Managing data systems to support semantic-independent schemas  
A method of maintaining data described in a plurality of data models. An ontology is used to describe the data models. The data models are managed using the ontology and using a validation schema...
8949545 Memory interface device and methods thereof  
A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device,...
8949547 Coherency controller and method for data hazard handling for copending data access requests  
A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. Write requests are processed in a two part form, such that a first part is...
8949540 Lateral castout (LCO) of victim cache line in data-invalid state  
A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect...
8949546 Network cache system for reducing redundant data  
Embodiments include a local cache management system that is configured to be coupled to a local cache and that includes an index engine configured to store fingerprints of message segments stored...
8943276 Efficient discard scans  
A plurality of tracks is examined for meeting criteria for a discard scan. In lieu of waiting for a completion of a track access operation, at least one of the plurality of tracks is marked for...
8938587 Data recovery for coherent attached processor proxy  
A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system...