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7624236 |
Predictive early write-back of owned cache blocks in a shared memory computer system
A method for predicting early write back of owned cache blocks in a shared memory computer system. This invention enables the system to predict which written blocks may be more likely to be...
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7624126 |
Registering for and retrieving database table change information that can be used to invalidate cache entries
A server provides Web responses that can include content from data tables in a database. The server maintains a cache (e.g., in system memory) that can store content (including content from data...
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7620696 |
System and method for conflict responses in a cache coherency protocol
A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response...
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7617365 |
Systems and methods to avoid deadlock and guarantee mirror consistency during online mirror synchronization and verification
Systems and methods can provide mirrored virtual targets and online synchronization and verification of the targets while avoiding deadlock, inconsistencies between members of the target, and false...
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7617329 |
Programmable protocol to support coherent and non-coherent transactions in a multinode system
A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol...
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7613886 |
Methods and apparatus for synchronizing data access to a local memory in a multi-processor system
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
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7613884 |
Multiprocessor system and method ensuring coherency between a main memory and a cache memory
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a...
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7613882 |
Fast invalidation for cache coherency in distributed shared memory system
An example embodiment of the present invention provides processes relating to a cache coherence protocol for distributed shared memory. In one process, a DSM-management chip receives a request to...
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7606979 |
Method and system for conservatively managing store capacity available to a processor issuing stores
Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter...
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7606978 |
Multi-node computer system implementing global access state dependent transactions
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to...
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7600149 |
Failure transparency for update applications under single-master configuration
A method masking data failures, when a master copy of data is unavailable comprises storing a single master copy of data and a replica copy of the data; writing to the master using a middleware...
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7600080 |
Avoiding deadlocks in a multiprocessor system
In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a...
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7600079 |
Performing a memory write of a data unit without changing ownership of the data unit
A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory...
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7600078 |
Speculatively performing read transactions
In one embodiment, the present invention includes a method for speculatively providing a read request to a memory controller associated with a processor, determining coherency of the read request...
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7596712 |
Method and system for efficiently accessing a storage redundancy group
A method and system for efficiently accessing a pool of mass storage devices are described. In one embodiment of the invention, a primary storage server and a secondary storage server share a pool...
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7596662 |
Selective storage of data in levels of a cache memory
In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the...
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7596570 |
Data sharing
In some embodiments, a method for detecting a shared data element comprises providing a first feature of a first data element associated with a first storage device; detecting a second feature of a...
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7594145 |
Improving performance of a processor having a defective cache
In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The...
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7590805 |
Monitor implementation in a multicore processor with inclusive LLC
A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always...
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7587556 |
Store buffer capable of maintaining associated cache information
A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer...
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7584329 |
Data processing system and method for efficient communication utilizing an Ig coherency state
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache...
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7581069 |
Multiple computer system with enhanced memory clean up
The updating of only some memory locations in a multiple computer environment in which at least one applications program ( 50 ) executes simultaneously on a plurality of computers M 1 , M 2 . . ....
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7581068 |
Exclusive ownership snoop filter
A snoop filter maintains data coherency information for multiple caches in a multi-processor system. The Exclusive Ownership Snoop Filter only stores entries that are exclusively owned by a...
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7581064 |
Utilizing cache information to manage memory access and cache utilization
In a method of utilizing cache metadata to optimize memory access, cache metadata associated with a set of cache locations is inspected by software. The cache metadata is analyzed to determine...
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7581056 |
Load balancing using distributed front end and back end virtualization engines
Methods and apparatus are provided for improving network virtualization in a storage area network. A virtualization engine is divided into a front end virtualization engine and a back end...
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7581042 |
I/O hub resident cache line monitor and device register update
The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a...
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7577797 |
Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response
A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first...
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7577795 |
Disowning cache entries on aging out of the entry
Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the...
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7577794 |
Low latency coherency protocol for a multi-chip multiprocessor system
Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels...
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RE40877 |
Method of communicating data in an interconnect system
A method is provided for communicating data in an interconnect system comprising a plurality of nodes. In one aspect, the method includes: issuing a command packet from a first node, the command...
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7574567 |
Monitoring processes in a non-uniform memory access (NUMA) computer system
A monitoring process for a NUMA system collects data from multiple monitored threads executing in different nodes of the system. The monitoring process executes on different processors in different...
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7574566 |
System and method for efficient software cache coherence
Software-based cache coherence protocol. A processing unit may execute a memory request using a processor thread. In response to detecting a cache hit to shared or a cache miss associated with the...
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7571288 |
Scalable rundown protection for object lifetime management
Object rundown protection that scales with the number of processors in a shared-memory computer system is disclosed. Prior to object rundown, a cache-aware reference count data structure is used to...
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7571286 |
Reduced memory traffic via detection and tracking of temporally silent stores
A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store,...
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7571285 |
Data classification in shared cache of multiple-core processor
In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class...
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7568072 |
Cache eviction
A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer...
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7562192 |
Microprocessor, apparatus and method for selective prefetch retire
An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system...
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7558913 |
Atomic commit of cache transfer with staging area
In a method of synchronizing with a separated disk cache, the separated cache is configured to transfer cache data to a staging area of a storage device. An atomic commit operation is utilized to...
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7552295 |
Maintaining consistency when mirroring data using different copy technologies
Provided are a method, system, and program for maintaining consistency when mirroring data using different copy technologies. Update groups having updates to primary storage locations are formed...
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7552288 |
Selectively inclusive cache architecture
In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the...
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7552247 |
Increased computer peripheral throughput by using data available withholding
A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and...
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7552223 |
Apparatus and method for data consistency in a proxy cache
In an embodiment, a method to provide data consistency in a storage system, includes: providing, by a server to a proxy cache, a lock associated with a delegated file in the server; in response to...
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7549025 |
Efficient marking of shared cache lines
One embodiment of the present invention provides a system that efficiently marks cache lines in a multi-processor computer system. The system starts by receiving a load request for a cache line...
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7549024 |
Multi-processing system with coherent and non-coherent modes
An integrated circuit comprising a plurality of processor cores operable to perform respective data processing operations, at least one of said processor cores being configurable to operate either...
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7548918 |
Techniques for maintaining consistency for different requestors of files in a database management system
A method and apparatus for providing file system operation locks at a database server is provided. A database server may employ database locks and file system operation locks in servicing requests...
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7546422 |
Method and apparatus for the synchronization of distributed caches
A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol...
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7546421 |
Interconnect transaction translation technique
A technique to reduce and simplify interconnect traffic within a multi-core processor. At least one embodiment translates two or more system operations destined for a processor core within a...
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7543121 |
Computer system allowing any computer to copy any storage area within a storage system
A computer system having a plurality of host computers and a storage system is provided which allows any one host computer to perform a global copy operation on any arbitrary or all storage areas...
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7543116 |
Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains
A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target...
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7543115 |
Two-hop source snoop based cache coherence protocol
A method for cache coherency in a network of a plurality of caching agents includes storing a plurality of miss requests, transmitting the miss requests into the network, sending a probe message on...
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