Matches 1 - 50 out of 249 1 2 3 4 5 >
Match Document Document Title
7617329 Programmable protocol to support coherent and non-coherent transactions in a multinode system  
A system includes a scalability port switch (SPS) and a plurality of nodes. The SPS has a plurality of ports, each port coupled to a node. Each port is connected to a scalability port protocol...
7594080 Temporary storage of memory line while waiting for cache eviction  
The temporary storage of a memory line to be stored in a cache while waiting for another memory line to be evicted from the cache is disclosed. A method includes evicting a first memory line...
RE40921 Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system  
A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it...
7552287 Method and system of controlling a cache memory by interrupting prefetch request with a demand fetch request  
A cache memory control unit that controls a cache memory comprises: a PF-PORT 22 and MI-PORT 21 that receive a prefetch request and demand fetch request issued from a primary cache; and a...
7543120 Processor and data processing system employing a variable store gather window  
A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue...
7543115 Two-hop source snoop based cache coherence protocol  
A method for cache coherency in a network of a plurality of caching agents includes storing a plurality of miss requests, transmitting the miss requests into the network, sending a probe message on...
7536509 Method for fetching data from a non-volatile memory in an integrated circuit and corresponding integrated circuit  
The method uses an integrated circuit comprising a processor ( 603 ), a non-volatile memory ( 602 ), especially a flash memory, a system clock and an interface ( 605 ), which is connected on the...
7526702 Method and system for testing a random access memory (RAM) device having an internal cache  
A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, the method comprising:...
7502892 Decoupling request for ownership tag reads from data read operations  
Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one...
7493621 Context switch data prefetching in multithreaded computer  
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
7487317 Cache-aware scheduling for a chip multithreading processor  
A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is...
7475210 Data stream generation method for enabling high-speed memory access  
An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit...
7464242 Method of load/store dependencies detection with dynamically changing address length  
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
7447845 Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality  
A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array,...
7447807 Systems and methods for storing data in segments of a storage subsystem  
A storage subsystem comprises a set of zone definitions that uses physical block addresses to divide a memory array in the storage subsystem into zones or segments. A set of zone parameters defines...
7401189 Pipelining D states for MRU steerage during MRU/LRU member allocation  
A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted...
7398358 Method and apparatus for high performance branching in pipelined microsystems  
A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions,...
7376793 Cache coherence protocol with speculative writestream  
A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to...
7370150 System and method for managing a cache memory  
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and...
7363468 Load address dependency mechanism system and method in a high frequency, low power processor system  
The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At...
7353310 Hierarchical memory access via pipelining with deferred arbitration  
A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline...
7302527 Systems and methods for executing load instructions that avoid order violations  
Methods for executing load instructions are disclosed. In one method, a load instruction and corresponding thread information are received. Address information of the load instruction is used to...
7269179 Control mechanisms for enqueue and dequeue operations in a pipelined network processor  
Common control for enqueue and dequeue operations in a pipelined network processor includes receiving in a queue manager a first enqueue or dequeue with respect to a queue and receiving a second...
7263585 Store-induced instruction coherency mechanism  
An apparatus and method for ensuring coherency of instructions within stages of the pipeline microprocessor. The apparatus includes instruction cache management logic and synchronization logic. The...
7243203 Pipeline circuit for low latency memory  
The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers...
7243192 Cache memory architecture with system controller device that compares cache tags to memory addresses received from microprocessor  
A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed...
7234027 Instructions for test & set with selectively enabled cache invalidate  
A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a...
7225300 Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system  
Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two...
7206230 Use of data latches in cache operations of non-volatile memories  
Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read...
7181575 Instruction cache using single-ported memories  
Systems, methodologies, media, and other embodiments associated with cache systems are described. One exemplary system embodiment includes an instruction cache comprising single-ported memories....
7177987 System and method for responses between different cache coherency protocols  
Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency...
7171535 Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline  
A general-purpose serial operation pipeline realizes a complicated processing flow with an extemporaneous and explosive amount of operations with respect to various data sizes. A plurality of...
7162618 Method for enhancing the visibility of effective address computation in pipelined architectures  
The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in...
7155574 Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory  
A high-speed memory management technique that minimizes clobber in sequentially accessed memory, including but not limited to, for example, a trace cache. The method includes selecting a victim set...
7146468 Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache  
A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query...
7143240 System and method for providing a cost-adaptive cache  
A cost-adaptive cache including the ability to dynamically maximize performance in a caching system by preferentially caching data according to the cost of replacing data. The cost adaptive cache...
7133968 Method and apparatus for resolving additional load misses in a single pipeline processor under stalls of instructions not accessing memory-mapped I/O regions  
An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor...
7130968 Cache memory architecture and associated microprocessor design  
A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high...
7124262 Selectivity pipelining and prefetching memory data  
A processor-based device (e.g., a wireless device) may include a processor and a semiconductor memory (e.g., a flash memory) to selectively pipeline and prefetch memory data, such as executable...
7111127 System for supporting unlimited consecutive data stores into a cache memory  
One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array...
7085885 Apparatus and method for early cache miss detection  
A cache memory that notifies other functional blocks in the microprocessor that a miss has occurred potentially N clocks sooner than the conventional method, where N is the number of stages in the...
7073026 Microprocessor including cache memory supporting multiple accesses per cycle  
A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a...
7047317 High performance network address processor system  
A high performance network address processor is provided comprising a longest prefix match lookup engine for receiving a request for data from a designated network destination address. An...
7039762 Parallel cache interleave accesses with address-sliced directories  
A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the...
7028141 High-speed distributed data processing system and method  
The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of conventional programming styles. The...
7013366 Parallel search technique for store operations  
A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. The present invention further relates to satisfying load operations faster than...
7003645 Use of a storage medium as a communications network for liveness determination in a high-availability cluster  
Liveness determination in a multinode data processing system is enhanced through the use of a shared nonvolatile memory, typically a disk, which is utilized in conjunction with defined transmission...
7000081 Write back and invalidate mechanism for multiple cache lines  
A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation...
6996665 Hazard queue for transaction pipeline  
A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another...
6996639 Configurably prefetching head-of-queue from ring buffers  
A method includes providing a prefetch cache of entries corresponding to communication rings stored in memory, the communication rings to store information passed from at least one first processing...
Matches 1 - 50 out of 249 1 2 3 4 5 >