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9037806 Reducing store operation busy times  
A computer product for reducing store operation busy times is provided. The computer product includes a tangible storage medium readable by a processing circuit and storing instructions for...
9015423 Reducing store operation busy times  
A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store...
9009415 Memory system including a spiral cache  
An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by...
8996819 Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy  
A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver....
8977815 Control of entry of program instructions to a fetch stage within a processing pipepline  
A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation...
8966181 Memory hierarchy with non-volatile filter and victim caches  
Various embodiments of the present invention are generally directed to an apparatus and method for non-volatile caching of data in a memory hierarchy of a data storage device. In accordance with...
8954681 Multi-stage command processing pipeline and method for shared cache access  
A command processing pipeline is coupled to a shared cache. The command processing pipeline comprises (i) a first command processing stage configured to sequentially receive and process first and...
8954666 Storage subsystem  
Provided is a storage subsystem capable of speeding up the input/output processing for a cache memory. Microprocessor Packages manage information related to a VDEV ownership for controlling...
8954674 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8930634 Speculative read in a cache coherent microprocessor  
A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent...
8930633 Reducing read latency using a pool of processing cores  
In a read processing storage system, using a pool of CPU cores, the CPU cores are assigned to process either write operations, read operations, and read and write operations, that are scheduled...
8924623 Method for managing multi-layered data structures in a pipelined memory architecture  
A method for managing multi-layered data structures in a pipelined memory architecture, comprising the steps of: —providing a multi-level data structure where each level corresponds to a memory...
8904109 Selective cache access control apparatus and method thereof  
A data processor is disclosed that definitively determines an effective address being calculated and decoded will be associated with an address range that includes a memory local to a data...
8862829 Cache unit, arithmetic processing unit, and information processing unit  
A cache unit comprising a register file that selects an entry indicated by a cache index of n bits (n is a natural number) that is used to search for an instruction cache tag, using multiplexer...
8838899 Internal processor buffer  
One or more of the present techniques provide a compute engine buffer configured to maneuver data and increase the efficiency of a compute engine. One such compute engine buffer is connected to a...
8838906 Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution  
In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory,...
8819360 Information processing apparatus, cache apparatus, and data processing method  
A more efficient technique is provided in an information processing apparatus which executes processing using pipelines. An information processing apparatus according to this invention includes a...
8805896 System and method for use with garbage collected languages for enabling the allocated heap memory to be updated at runtime  
A system and method for use with garbage collected systems and languages, for enabling an allocated heap memory to be updated (e.g., increased or decreased) at runtime, subject to sufficient...
8782346 Dynamic prioritization of cache access  
Some embodiments of the inventive subject matter are directed to determining that a memory access request results in a cache miss and determining an amount of cache resources used to service cache...
8775717 Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories  
A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a...
8769211 Monitoring thread synchronization in a distributed cache  
Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread...
8769210 Dynamic prioritization of cache access  
Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an...
8762620 Multiprocessor storage controller  
A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In...
8751755 Mass storage controller volatile memory containing metadata related to flash memory storage  
A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage,...
8745312 Storage device and method of mapping a nonvolatile memory based on a map history  
A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A...
8738863 Configurable multi-level buffering in media and pipelined processing components  
Methods and apparatus relating to buffering in media and pipelined processing components are described. In one embodiment, a buffer may include an arbiter to receive data structure information...
8738841 Flash memory controller and system including data pipelines incorporating multiple buffers  
A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is...
8732407 Deadlock avoidance during store-mark acquisition  
Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark...
8706972 Dynamic mode transitions for cache instructions  
A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter, selecting one of the plurality of requests as a...
8671245 Using identification in cache memory for parallel requests  
In an exemplary computer system having one or more masters configured to the same slave memory using a protocol, such as the AMBA AXI protocol, a master provides an ID field to the memory as part...
8667223 Shadow registers for least recently used data in cache  
A cache for use in a central processing unit (CPU) of a computer includes a data array; a tag array configured to hold a list of addresses corresponding to each data entry held in the data array;...
8645796 Dynamic pipeline cache error correction  
Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline...
8639887 Dynamically altering a pipeline controller mode based on resource availability  
A mechanism for dynamically altering a request received at a hardware component is provided. The request is received at the hardware component, and the request includes a mode option. It is...
8635409 Dynamic mode transitions for cache instructions  
A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter; selecting one of the plurality of requests as a...
8612690 Method for filtering traffic to a physically-tagged data cache  
Embodiments of a data cache are disclosed that substantially decrease a number of accesses to a physically-tagged tag array of the data cache are provided. In general, the data cache includes a...
8566532 Management of multipurpose command queues in a multilevel cache hierarchy  
An apparatus for controlling access to a pipeline includes a plurality of command queues including a first subset of the plurality of command queues being assigned processes the commands of first...
8549235 Method for detecting address match in a deeply pipelined processor design  
A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the...
8543768 Memory system including a spiral cache  
An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by...
8533400 Selective memory access to different local memory ports and method thereof  
A data processor is disclosed that definitively determines an effective address being calculated and decoded will be associated with an address range that includes a memory local to a data...
8533163 Database offload processing  
Handling a database request includes providing a first database manager on a storage device containing data for the database, generating the database request external to the storage device,...
8521960 Mitigating busy time in a high performance cache  
A method, information processing device, and computer program product mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated...
8516149 System for operating NFSv2 and NFSv3 clients with federated namespace  
An information retrieval system having: a client adapted for accessing a plurality of file sets stored on one of a plurality of file servers; a plurality of file servers configured to operate with...
8499123 Multi-stage pipeline for cache access  
Embodiments of the present disclosure provide a command processing pipeline operatively coupled to an N-way cache and configured to process a sequence of cache commands. A way of the N ways of the...
8473711 Apparatus for predicting memory access and method thereof  
A method for predicting memory access, where each data processing procedure is performed in a plurality of stages with segment processing, and the plurality of stages include at least a first...
8468306 Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions  
A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent...
8438003 Methods for improved simulation of integrated circuit designs  
A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy...
8407420 System, apparatus and method utilizing early access to shared cache pipeline for latency reduction  
A memory system, apparatus and method for performing operations in a shared cache coupled to a first requester and a second requester. The method includes receiving at the shared cache a first...
8386687 Method and apparatus for data transfer  
A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the...
8370582 Merging subsequent updates to a memory location  
A method of merging subsequent updates to a memory location includes receiving, at a first stage in an update pipeline, a first request to update a status word at a first address of a cache memory...
8352687 Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy  
A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver....

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