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7631149 |
Systems and methods for providing fixed-latency data access in a memory system having multi-level caches
Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible...
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7610469 |
Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the...
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7600078 |
Speculatively performing read transactions
In one embodiment, the present invention includes a method for speculatively providing a read request to a memory controller associated with a processor, determining coherency of the read request...
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7594081 |
Direct access to low-latency memory
A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system...
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7590884 |
Storage system, storage control device, and storage control method detecting read error response and performing retry read access to determine whether response includes an error or is valid
In a storage system, a disk device performs recovery and transfers read data to a control device, and the control device judges the validity of the recovery to prevent a transfer of erroneous data....
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7587555 |
Program thread synchronization
The present invention is a method of and system for program thread synchronization. In accordance with an embodiment of the invention, a method of synchronizing program threads for one or more...
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7577791 |
Virtualized load buffers
A memory addressing technique using load buffers is described. More particularly, embodiments of the invention relate to a method and apparatus for accessing data in a computer system by exploiting...
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7519774 |
Data processor having a memory control unit with cache memory
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
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7506119 |
Complier assisted victim cache bypassing
A method for compiler assisted victim cache bypassing including: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a...
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7502903 |
Method and apparatus for managing data storage systems
A method is provided for a data storage system to move data from a source logical disk (LD) region to a target LD region while the data storage system remains online to a host. The method includes...
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7502892 |
Decoupling request for ownership tag reads from data read operations
Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one...
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7467377 |
Methods and apparatus for compiler managed first cache bypassing
Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is...
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7466647 |
Efficient muxing scheme to allow for bypass and array access
A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required...
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7467129 |
Method and apparatus for latency and power efficient database searches
Methods, apparatus and systems perform searches in a CAM memory that is divided into one or more databases. A selector selects at least two the databases for a simultaneous search, and selects at...
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7464077 |
Queryable cache in real-time data management system
In order to provide real-time data analysis of high speed data, a query control mechanism may be provided and coupled to one or more caches. The caches may temporarily store the incoming high-speed...
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7464226 |
Fractional caching
A microprocessor-based system generates an electronic document based on a set of microprocessor-readable instructions organized in logical units known as instruction nodes. Each instruction node...
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7461187 |
Bus system and data transfer method
A bus system which transfers data from a first device to a second device includes a holding unit which holds data input from the first device, and a selecting unit which selects whether to output...
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7430641 |
System method and circuit for retrieving into cache data from one or more mass data storage devices
According to some embodiments of the present invention, a data storage system may include a plurality of controllers connected or otherwise associated with one or more mass data storage devices....
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7421726 |
Method of seamlessly replacing disc-based video streams with memory-based video streams in a video-on-demand system
In a video-on-demand system, disc-based video streams are seamlessly replaced with memory-based video streams. This is achieved by first switching each disc-based video stream to a mixed video...
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7401188 |
Method, device, and system to avoid flushing the contents of a cache by not inserting data from large requests
A method, device, and system are disclosed. In one embodiment, the method comprises setting a threshold length for data allowed in a cache, inserting data into the cache during a read or a write...
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7401187 |
Method and apparatus for reading a data store
In an electronic computing system, an instruction is provided as to whether to cache in a region of a memory of the system an attribute of a context if and when the context is accessed in a...
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7395381 |
Method and an apparatus to reduce network utilization in a multiprocessor system
A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor...
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7392350 |
Method to operate cache-inhibited memory mapped commands to access registers
In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the...
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7380067 |
IO-stream adaptive write caching policy adjustment
A method for performing adaptive write caching in a storage virtualization subsystem is disclosed. In this method, criteria associated with an operation state of the storage virtualizalion...
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7376807 |
Data processing system having address translation bypass and method therefor
In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method...
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7360015 |
Preventing storage of streaming accesses in a cache
In one embodiment of the present invention, a method may include determining whether requested information is part of a streaming access, and directly writing the requested information from a...
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7360020 |
Method for improving cache-miss performance
A cache memory with improved cache-miss performance is implemented by providing cache-miss data from system memory directly to its requester. One embodiment of the invention operates as a texture...
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7356650 |
Cache apparatus and method for accesses lacking locality
Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a...
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7356649 |
Semiconductor data processor
A semiconductor data processor has a first memory( 6 ) constituting a cache memory, a second memory( 20 ) capable of being a cacheable area or a non-cacheable area by the first memory, and a read...
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7353445 |
Cache error handling in a multithreaded/multi-core processor
In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error...
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7349942 |
Storage medium having a manageable file directory structure
A file-mapping method and system can better manage the number of items (i.e., files, subdirectories, or a combination of them) within any single directory within a storage medium. The method and...
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7346743 |
Excluding a toggle bit from the range of cacheable addresses in a flash memory
In a method and arrangement for manipulation of the contents of a data memory with which a processing device can be connected to manipulate (in at least one manipulation step at least one first...
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7346735 |
Virtualized load buffers
A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access...
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7346742 |
Methods and structure for bypassing memory management mapping and translation features
Methods and associated structures for bypassing virtual memory and memory mapping management features provided in a memory controller applied to simpler computing applications. In one aspect...
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7318118 |
System and method for selective write to flash memory in HDD
For non-bursty data writes, data is written to flash memory of a hard disk drive for subsequent de-staging to disk, whereas for bursty writes data is written directly to disk.
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7302528 |
Caching bypass
In general, in one aspect, the disclosure describes a method that includes providing a memory access instruction of a processing element's instruction set including multiple parameters. The...
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7278013 |
Apparatus having a cache and a loop buffer
Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.
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7275136 |
Virtualization system for computers with a region-based memory architecture
In a computer system with a non-segmented, region-based memory architecture, such as Intel IA-64 systems, two or more sub-systems share a resource, such as a virtual-to-physical address mapping and...
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7246205 |
Software controlled dynamic push cache
Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters...
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7243203 |
Pipeline circuit for low latency memory
The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers...
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7237065 |
Configurable cache system depending on instruction type
A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic...
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7234026 |
Media player with instant play capability
A media player and a method for operating a media player are disclosed. A media program is able to substantially immediately begin playing after a media play selection has been made. Through...
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7228388 |
Enabling and disabling cache bypass using predicted cache line usage
Arrangements and method for enabling and disabling cache bypass in a computer system with a cache hierarchy. Cache bypass status is identified with respect to at least one cache line. A cache line...
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7228386 |
Programmably disabling one or more cache entries
A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be...
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7216149 |
Gathering enriched web server activity data of cached web content
A method and system for gathering enriched web server activity data in a global communications network in which requested information files are cached at a plurality of network devices. With the...
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7203800 |
Narrow/wide cache
A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and...
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7197602 |
Multiple cache communication and uncacheable objects
The invention provides a method and system for operating multiple communicating caches. Between caches, unnecessary transmission of repeated information is substantially reduced. Each cache...
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7194576 |
Fetch operations in a disk drive control system
A method and system for improving fetch operations between a micro-controller and a remote memory via a buffer manager in a disk drive control system comprising a micro-controller, a...
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7167952 |
Method and system for performing a memory-mode write to cache
A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent,...
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7165144 |
Managing input/output (I/O) requests in a cache memory system
Provided are a method, system, and program for managing Input/Output (I/O) requests in a cache memory system. A request is received to data at a memory address in a first memory device, wherein...
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