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8209489 Victim cache prefetching  
A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy...
8209488 Techniques for prediction-based indirect data prefetching  
A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a...
8200906 Cache structure for peer-to-peer distribution of digital objects  
A method for the distribution of digital objects in a peer-to-peer network is disclosed. The digital objects are distributed in a plurality of pieces. At least some of a plurality of peers are...
8200905 Effective prefetching with multiple processors and threads  
A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a...
8195918 Memory hub with internal cache and/or memory access prediction  
A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled...
8195884 Network on chip with caching restrictions for pages of computer memory  
A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through...
8195889 Hybrid region CAM for region prefetcher and methods thereof  
A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second...
8195888 Multiprocessor cache prefetch with off-chip bandwidth allocation  
Technologies are generally described for allocating available prefetch bandwidth among processor cores in a multiprocessor computing system. The prefetch bandwidth associated with an off-chip...
8190824 Cache line replacement monitoring and profiling  
Systems and methods for cache replacement monitoring (CRM) are provided. The system includes a monitored cache comprising a monitored cache line set, the monitored cache line set comprising at...
8190825 Arithmetic processing apparatus and method of controlling the same  
A common L2 cache unit of a CPU constituting a multicore processor, in addition to a PFPORT arranged for each CPU core unit, has a common PFPORT shared by the plurality of the CPU core units. The...
8185696 Virtual memory window with dynamic prefetching support  
Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic,...
8176254 Specifying an access hint for prefetching limited use data in a cache hierarchy  
A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the...
8171266 Look-ahead load pre-fetch in a processor  
A method for look-ahead load pre-fetching that reduces the effects of instruction stalls caused by high latency instructions. Look-ahead load pre-fetching is accomplished by searching an...
8171102 Smart access to a dispersed data storage network  
A method for reading data from a dispersed data storage network that includes a plurality of slice servers. The method begins by accessing a list of slice servers of the plurality of slice...
8171226 Method and apparatus for execution of a process  
Techniques are provided for enabling execution of a process employing a cache Method steps can include obtaining a first probability of accessing a given artifact in a state Si, obtaining a second...
8171224 D-cache line use history based done bit based on successful prefetchable counter  
A method of providing history based done logic for a D-cache includes receiving a D-cache line in an L2 cache; determining if the D-cache line is unprefetchable; aging the D-cache line without a...
8166229 Apparatus and method for multi-level cache utilization  
In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic...
8166259 Memory control apparatus, memory control method and information processing system  
A memory control apparatus, a memory control method and an information processing system are disclosed. Fetch response data retrieved from a main storage unit is received, while bypassing a...
8166252 Processor and prefetch support program  
A processor loads a program from a main memory, detects a register updating instruction, and registers the address of the register updating instruction in a register-producer table storing unit....
8166251 Data prefetcher that adjusts prefetch stream length based on confidence  
In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to identify a prefetch stream in cache misses from the data...
8166250 Information processing unit, program, and instruction sequence generation method  
An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address...
8161245 Method and apparatus for performing data prefetch in a multiprocessor system  
A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory...
8161246 Prefetching of next physically sequential cache line after cache line that includes loaded page table entry  
A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load...
8156287 Adaptive data prefetch  
A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode....
8156286 Processor and method for using an instruction hint to prevent hardware prefetch from using certain memory accesses in prefetch calculations  
A microprocessor includes a cache memory, a prefetch unit, and detection logic. The prefetch unit may be configured to monitor memory accesses that miss in the cache and to determine whether to...
8151084 Using address and non-address information for improved index generation for cache memories  
Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes...
8151102 System and methods for booting electronic devices  
The invention provides a boot method capable of reducing boot time even in the case of a change in the configuration of boot files. A boot file is booted from a hard disk drive in a computer...
8151055 Cache accessing using a micro TAG  
A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache...
8145846 Memory system having nonvolatile and buffer memories, and reading method thereof  
Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request...
8145849 Wake-and-go mechanism with system bus response  
A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target...
8140760 I-cache line use history based done bit based on successful prefetchable counter  
A method of providing history based done logic for a I-cache includes receiving an I-cache line in an L2 cache; determining if the I-cache line is unprefetchable; aging the I-cache line without a...
8140769 Data prefetcher  
In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to detect one or more prefetch streams corresponding to load...
8140801 Efficient and flexible memory copy operation  
A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a...
8140757 Network acceleration and long-distance pattern detection using improved caching and disk mapping  
A compression device recognizes patterns of data and compressing the data, and sends the compressed data to a decompression device that identifies a cached version of the data to decompress the...
8140768 Jump starting prefetch streams across page boundaries  
A method, processor, and data processing system for enabling utilization of a single prefetch stream to access data across a memory page boundary. A prefetch engine includes an active streams...
8135915 Method and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicator  
A method, apparatus, and computer instructions for providing hardware assistance to prefetch data during execution of code by a process or in the data processing system. In response to loading an...
8135933 Adaptive memory system for enhancing the performance of an external computing device  
An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static...
8131938 Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems  
In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later...
8127080 Wake-and-go mechanism with system address bus transaction master  
A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target...
8127081 Memory hub and access method having internal prefetch buffers  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory...
8127108 Apparatus, system and method for prefetching data in bus system  
A method for prefetching data in a bus system is provided. First, according to an address signal from a master, a prefetching address generator generates a prefetching address signal and transfers...
8122196 System and procedure for rapid decompression and/or decryption of securely stored data  
A procedure and system reduces latency in restoring encrypted or compressed and encrypted data through a security appliance. The security appliance is coupled to a sequential access device and is...
8117398 Prefetch termination at powered down memory bank boundary in shared memory controller  
A prefetch scheme in a shared memory multiprocessor disables the prefetch when an address falls within a powered down memory bank. A register stores a bit corresponding to each independently...
8112587 Shared data prefetching with memory region cache line monitoring  
A method, circuit arrangement, and design structure for prefetching data for responding to a memory request, in a shared memory computing system of the type that includes a plurality of nodes, is...
8108617 Method to bypass cache levels in a cache coherent system  
Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass...
8108616 Processing a data stream by accessing one or more hardware registers  
Disclosed are a method, a system, and a program product for processing a data stream by accessing one or more hardware registers of a processor. In one or more embodiments, a first program...
8108615 Prefetching controller using a counter  
A pre-fetch controller for pre-fetching data from a memory and providing data to a logic operation unit is disclosed. The pre-fetch controller includes a register for storing a counter value and a...
8108457 Methods and apparatus to enhance the performance of web browsers over bandwidth constrained links  
Increasing the performance of a browser while operating over bandwidth constrained links by pre-fetching of web objects to increase the level of concurrency. Using an agent or a gateway to speed...
8103832 Method and apparatus of prefetching streams of varying prefetch depth  
Method and apparatus of prefetching streams of varying prefetch depth dynamically changes the depth of prefetching so that the number of multiple streams as well as the hit rate of a single stream...
8094160 Moving-picture processing apparatus and pre-fetch control method  
A moving-picture processing apparatus has a pre-fetch memory pre-fetching a portion of a decoded picture stored in an external memory, and a miss/hit determination unit determining a manner in...