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8370581 System and method for dynamic data prefetching  
According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination...
8364901 Memory prefetch systems and methods  
Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline...
8364902 Microprocessor with repeat prefetch indirect instruction  
A microprocessor includes an instruction decoder for decoding a repeat prefetch indirect instruction that includes address operands used to calculate an address of a first entry in a prefetch...
8359430 Techniques for efficient mass storage layout optimization  
A data storage system can automatically improve the layout of data blocks on a mass storage subsystem by collecting optimization information during both read and write activities, then processing...
8359438 Memory banking system and method to increase memory bandwidth via parallel read and write operations  
A cache memory and a tag memory are included in a banked memory system and used to effectively enable parallel write and read operations on each clock cycle, even though the memory banks consist...
8359435 Optimization of software instruction cache by line re-ordering  
A method for computing includes executing a program, including multiple cacheable lines of executable code, on a processor having a software-managed cache. A run-time cache management routine...
8356143 Prefetch mechanism for bus master memory access  
A system and method for optimizing memory bus bandwidth, is achieved by utilization of the memory bus, either by utilizing the idle time of the memory bus, or by prioritizing prefetch requests to...
8356142 Memory controller for non-sequentially prefetching data for a processor of a computer system  
A memory controller for non-sequentially prefetching data for a processor of a computer system. The memory controller performs a method including the step of storing a plurality of address pairs...
8352686 Method and system for data prefetching for loops based on linear induction expressions  
An efficient and effective compiler data prefetching technique is disclosed in which memory accesses may be prefetched are represented in linear induction expressions. Furthermore, indirect memory...
8347039 Programmable stream prefetch with resource optimization  
A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine evaluates whether a first memory address...
8347037 Victim cache replacement  
A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that...
8341357 Pre-fetching for a sibling cache  
One embodiment provides a system that pre-fetches into a sibling cache. During operation, a first thread executes in a first processor core associated with a first cache, while a second thread...
8332570 Methods and systems for defragmenting virtual machine prefetch data on physical storage  
A computer-implemented method for defragmenting virtual machine prefetch data. The method may include obtaining prefetch information associated with prefetch data of a virtual machine. The method...
8327077 Method and apparatus of parallel computing with simultaneously operating stream prefetching and list prefetching engines  
A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and...
8316188 Data prefetch unit utilizing duplicate cache tags  
In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each...
8316187 Cache memory including a predict buffer  
Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache...
8312223 Pre-fetching virtual environment in a virtual universe based on previous traversals  
An approach is provided for pre-fetching of virtual content in a virtual universe based on previous traversals. In one embodiment, there is a pre-fetching tool, including a ranking component...
8307163 Hybrid density memory storage device  
The present invention discloses a hybrid density memory storage device configured to store data responsive to a host and a file system thereof. The hybrid density memory storage device includes a...
8307156 Adaptively modifying pre-read operations within a rotating media storage device  
A rotating media storage device (RMSD) that adaptively modifies pre-read operations is disclosed. The RMSD schedules a pre-read data segment on a second track of disk, commands a movable head to...
8307164 Automatic determination of read-ahead amount  
Read-ahead of data blocks in a storage system is performed based on a policy. The policy is stochastically selected from a plurality of policies in respect to probabilities. The probabilities are...
8296353 Flow control method and apparatus for enhancing the performance of web browsers over bandwidth constrained links  
Flow control is applied to increasing the performance of a browser while pre-fetching Web objects while operating over bandwidth constrained links to increase the level of concurrency, thus...
8290349 Playback apparatus, method, and program  
The present invention relates to a playback apparatus, a method, and a program which can appropriately perform jump playback when content transmitted through a network is played back in real time....
8291171 Altering prefetch depth based on ready data  
A system comprises a controller and a buffer accessible to the controller. The controller is configured to prefetch data from a storage medium in advance of such prefetch data being requested by a...
8291172 Multi-modal data prefetcher  
A microprocessor includes first and second cache memories occupying distinct hierarchy levels, the second backing the first. A prefetcher monitors load operations and maintains a recent history of...
8285971 Block driven computation with an address generation accelerator  
A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at...
8285930 Methods for adapting performance sensitive operations to various levels of machine loads  
For each of a plurality of memory access routines having different access timing characteristic, a redundant array of independent disk (RAID) stack executes the memory access routine to load...
8285941 Enhancing timeliness of cache prefetching  
A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a...
8284772 Method for scheduling a network packet processor  
A method is provided for scheduling a network packet processor. A textual language specification is input of the processing of network packets by the network packet processor. The textual language...
8281078 Multi-level cache prefetch  
Methods and apparatus relating to multi-level cache prefetch are described. In some embodiments, a data parking logic updates a prefetch request with one or more bits based on the status of a...
8275946 Channel tags in memory components for optimizing logical to physical address translations  
A method and system for performing logical to physical address translations in a memory is disclosed, wherein the memory includes a translation cache containing a subset of a plurality of entries...
8271750 Entry replacement within a data store using entry profile data and runtime performance gain data  
A data processing system includes a data store having storage locations storing entries which can be used for a variety of purposes, such as operand value prediction, branch prediction, etc. An...
8266381 Varying an amount of data retrieved from memory based upon an instruction hint  
In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the...
8261257 Method and apparatus for transferring firmware between an operating system and a device in a host  
A host system includes an operating system having a user space and a kernel space with a memory. A device driver performs download cycles to download a firmware file from the user space to the...
8261316 System for accessing a data set on the basis of A-priori knowledge of an interconnection of a plurality of corresponding data files in response to an access message from a client to a master  
A system (1) for storing and/or retrieving a data-set is proposed, wherein the data-set comprises a plurality of data-files, the system comprising: storage(3) for storing the data-set; at least...
8255634 Apparatus and methods for look-ahead virtual volume meta-data processing in a storage controller  
Apparatus and methods for improved efficiency in accessing meta-data in a storage controller of a virtualized storage system. Features and aspects hereof walk/retrieve meta-data for one or more...
8255633 List based prefetch  
A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current...
8255631 Priority-based prefetch requests scheduling and throttling  
A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a...
8255632 Pre-fetch control apparatus  
A pre-fetch control apparatus is equipped with a next-line pre-fetch control apparatus 38. An address overflowed from a pre-fetch address queue 26 is stored in the next-line pre-fetch control...
8250307 Sourcing differing amounts of prefetch data in response to data prefetch requests  
According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested...
8244963 Method for giving read commands and reading data, and controller and storage system using the same  
A method for giving a read command to a flash memory chip to read data to be accessed by a host system is provided. The method includes receiving a host read command; determining whether the...
8234454 Method and system of numerical analysis for continuous data  
A method of numerical analysis for continuous data includes: providing a temporary storage block, fetching a plurality of data units sequentially from continuous data to store in the temporary...
8230177 Store prefetching via store queue lookahead  
Systems and methods for efficient handling of store misses. A processor comprises a store queue that stores data for committed store instructions. Coupled to the store queue is a cache responsible...
8225072 Pre-fetching data into a memory  
Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or...
8225070 Information processing apparatus and cache memory control method  
An information processing apparatus including a main memory and a processor, the processor includes: a cache memory that stores data fetched to the cache memory; an instruction processing unit...
8225047 Memory system with pre-fetch operation  
A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing...
8219934 Method and code module for facilitating navigation between webpages  
A method (104), operable on a processor platform (24), and a code module (38) facilitate navigation between webpages (34) of a website (32). The code module (38) is incorporated into the webpages...
8219722 DMA and graphics interface emulation  
An emulator schedules emulation threads for DMA emulation and other emulation functions in a time-multiplexed manner. Emulation threads are selected for execution according to a load balancing...
8214599 Storage device prefetch system using directed graph clusters  
A system analyzes access patterns in a storage system. Logic circuitry in the system identifies different address regions of contiguously accessed memory locations. A statistical record identifies...
8214608 Behavioral monitoring of storage access patterns  
A storage control system monitors storage operations directed to storage blocks in a storage device. The storage control system uses arrays of counters to track a number of the storage operations,...
8214597 Cache tentative read buffer  
An apparatus having a cache and a circuit. The cache may store old lines having old instructions. The circuit may (i) receive a first read command, (ii) fetch-ahead a new line having new...