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8707014 Arithmetic processing unit and control method for cache hit check instruction execution  
According to an aspect of an embodiment of the invention, an arithmetic processing unit includes a first cache memory unit that holds a part of data stored in a storage device; an address register...
8700859 Transfer request block cache system and method  
The present invention is directed to a transfer request block (TRB) cache system and method. A cache is used to store plural TRBs, and a mapping table is utilized to store corresponding TRB...
8700860 Information processing apparatus, method and computer program  
An information processing apparatus for processing input data using multiple items of reference data in succession is provided. The apparatus includes a secondary storage unit configured to store...
8694750 Method and system for data structure management  
Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the...
8694584 Speculative and coordinated data access in a hybrid memory server  
A method, accelerator system, and computer program product, for prefetching data from a server system in an out-of-order processing environment. A plurality of prefetch requests associated with...
8689210 Service node, network, and method for pre-fetching for remote program installation  
A system for a package pre-fetching for a remote program installation. The system includes a cache and a service program unit. The service program unit receives a request for a package required...
8688944 Memory sharing between embedded controller and central processing unit chipset  
An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a...
8688960 Managing migration of a prefetch stream from one processor core to another processor core  
A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special...
8688961 Managing migration of a prefetch stream from one processor core to another processor core  
A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special...
8683133 Termination of prefetch requests in shared memory controller  
A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids...
8683136 Apparatus and method for improving data prefetching efficiency using history based prefetching  
An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in...
8683134 Upgrade of low priority prefetch requests to high priority real requests in shared memory controller  
A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes...
8683137 Cache pre-allocation of ways for pipelined allocate requests  
This invention is a data processing system with a data cache. The cache controller responds to a cache miss requiring allocation by pre-allocating a way in the set to an allocation request...
8683135 Prefetch instruction that ignores a cache hit  
Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution...
8683140 Cache-based speculation of stores following synchronizing operations  
A method of processing store requests in a data processing system includes enqueuing a store request in a store queue of a cache memory of the data processing system. The store request identifies...
8683138 Instruction for pre-fetching data and releasing cache lines  
A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of...
8683132 Memory controller for sequentially prefetching data for a processor of a computer system  
A memory controller for prefetching data for a processor, or CPU, of a computer system. The memory controller functions by interfacing the processor to system memory via a system memory bus. A...
8671246 Information processing system and information processing method  
An information processing system performs a prefetch for predicting data that is likely to be accessed by a central processing unit, reading the predicted data from a main memory, and storing the...
8667225 Store aware prefetching for a datastream  
A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor...
8667224 Techniques for data prefetching  
Described are techniques for processing a data operation in a data storage system. A front-end component of the data storage system receives the data operation. In response to receiving the data...
8661067 Predictive migrate and recall  
Various embodiments for optimizing data migration and recall in a computing storage environment by a processor device are provided. Data stored in the computing storage environment is analyzed...
8661203 Efficient track destage in secondary storage  
For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary...
8656112 Checkpointed tag prefetcher  
A dual-mode prefetch system for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags identifying the data stored in the...
8656088 Optimized flash based cache memory  
Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory...
8656111 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Bounding box prefetcher
 
A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing...
8650364 Processing system with linked-list based prefetch buffer and methods for use therewith  
A processing device includes a memory and a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to...
8650380 Processor and arithmatic operation method  
A processor has a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address. The processor determines, when a target...
8645630 Stream context cache system  
The present invention is directed to a stream context cache system, which primarily includes a cache and a mapping table. The cache stores plural stream contexts, and the mapping table stores...
8645404 Memory pattern searching via displaced-read memory addressing  
A split data word including a portion of each of two word-aligned data words stored at two word-aligned address boundaries within a memory is read from a displaced-read memory address relative to...
8645631 Combined L2 cache and L1D cache prefetcher  
A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the...
8645619 Optimized flash based cache memory  
Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory...
8639886 Store-to-load forwarding mechanism for processor runahead mode operation  
A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor...
8639870 String searching within peripheral storage devices  
Systems and methods for retrieving data stored on a peripheral storage device such as a magnetic tape drive or disk drive include string searching using the peripheral storage device resources...
8635406 Data processing apparatus and method for providing target address information for branch instructions  
A data processing apparatus and method have a processor for executing instructions, and a prefetch unit for prefetching instructions from memory prior to sending those instructions to the...
8635408 Controlling power of a cache based on predicting the instruction cache way for high power applications  
A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code....
8627013 Methods and systems for caching data using behavioral event correlations  
A method is disclosed including a client accessing a cache for a value of an object based on an object identification (ID), initiating a request to a cache loader if the cache does not include a...
8627021 Method and apparatus for load-based prefetch access  
A load state of a slave memory is detected and provided to a master device. The master device communicates prefetch access requests to the slave memory based, at least in part, on the detected...
8621157 Cache prefetching from non-uniform memories  
An apparatus is disclosed for performing cache prefetching from non-uniform memories. The apparatus includes a processor configured to access multiple system memories with different respective...
8615583 Systems and methods of revalidating cached objects in parallel with request for object  
The present solution provides a variety of techniques for accelerating and optimizing network traffic, such as HTTP based network traffic. The solution described herein provides techniques in the...
8607005 Monitoring program execution to learn data blocks accessed by software process for facilitating efficient prefetching  
An apparatus, system, and method are disclosed for determining prefetch data. A start module communicates a start of a target software process to a storage device. A learning module learns data...
8607002 Memory prefetch systems and methods  
Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline...
8595471 Executing repeat load string instruction with guaranteed prefetch microcode to prefetch into cache for loading up to the last value in architectural register  
A microprocessor invokes microcode in response to encountering a repeat load string instruction. The microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into a...
8595443 Varying a data prefetch size based upon data usage  
A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data...
8595444 Processing read requests by a storage system  
Read messages are issued by a client for data stored in a storage system. A client agent mediates between the client and the storage system. Each sequence of read requests generated by a single...
8589632 Arbitration method for programmable multiple clock domain bi-directional interface  
An embodiment of the present invention is directed to a system including a memory interface logic unit for receiving memory access requests and corresponding information, a processor coupled to...
8581754 Encoding and decoding to reduce switching of flash memory transistors  
Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating...
8583894 Hybrid prefetch method and apparatus  
A hybrid prefetch method and apparatus is disclosed. A processor includes a hybrid prefetch unit configured to generate addresses for accessing data from a system memory. The hybrid prefetch unit...
8583874 Method and apparatus for caching prefetched data  
A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache...
8578102 Determining data contents to be loaded into a read-ahead cache in a storage system  
Read messages are issued by a client for data stored in a storage system of the networked client-server architecture. A client agent mediates between the client and the storage system. Each...
8578097 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...