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8880847 Multistream prefetch buffer  
A prefetching system receives a memory read request having an associated address. In response to a determination that a most significant portion of the associated address is not present within...
8872677 Method and apparatus for compressing data-carrying signals  
A compression method applies a selection rule to input symbols and generates a reduced partial set of symbols. The partial set is checked against a dictionary-index for a match. A match identifies...
8874853 Local and global memory request predictor  
A method, circuit arrangement, and design structure utilize broadcast prediction data to determine whether to globally broadcast a memory request in a computing system of the type that includes a...
8874840 Adaptive prestaging in a storage controller  
In one aspect of the present description, at least one of the value of a prestage trigger and the value of the prestage amount, may be modified as a function of the drive speed of the storage...
8868822 Data-processing method, program, and system  
A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and...
8862831 Method and apparatus to facilitate shared pointers in a heterogeneous platform  
A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to,...
8856453 Persistent prefetch data stream settings  
A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication...
8856447 Converting memory accesses near barriers into prefetches  
Methods, apparatuses, and processors for reducing memory latency in the presence of barriers. When a barrier operation is executed, subsequent memory access operations are delayed until the...
8856454 Anticipatory response pre-caching  
Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or...
8856452 Timing-aware data prefetching for microprocessors  
A method and apparatus for prefetching data from memory for a multicore data processor. A prefetcher issues a plurality of requests to prefetch data from a memory device to a memory cache....
8856451 Method and apparatus for adapting aggressiveness of a pre-fetcher  
The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from...
8850124 Method, system, apparatus, and computer-readable medium for implementing caching in a storage system  
A method, system, apparatus, and computer-readable medium are provided for performing read-ahead operations for sequential read operations. A method includes maintaining a bitmap including a...
8850123 Cache prefetch learning  
An apparatus generally having a processor, a cache and a circuit is disclosed. The processor may be configured to generate (i) a plurality of access addresses and (ii) a plurality of program...
8850116 Data prefetch for SCSI referrals  
A method for communication between an initiator system and a storage cluster. The method comprises receiving an initial I/O request from the initiator system to a first storage system; providing a...
8850118 Circuit and method for dynamically changing reference value for address counter based on cache determination  
A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value...
8838906 Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution  
In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory,...
8832385 Read-ahead processing in networked client-server architecture  
Read messages are grouped by a plurality of unique sequence identifications (IDs), where each of the sequence IDs corresponds to a specific read sequence, consisting of all read and read-ahead...
8832415 Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests  
A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one...
8832384 Reassembling abstracted memory accesses for prefetching  
A storage proxy receives different abstracted memory access requests that are abstracted from the original memory access requests from different sources. The storage proxy reconstructs the...
8831229 Key transport method, memory controller and memory storage apparatus  
A key transport method for transporting a key from a buffer memory to an encryption/decryption unit is provided. The method includes logically dividing bits of the key into key segments, wherein...
8819390 Speculative reads  
Patterns of access and/or behavior can be analyzed and persisted for use in pre-fetching data from a physical storage device. In at least some embodiments, data can be aggregated across volumes,...
8812790 Caching based on spatial distribution of accesses to data storage devices  
A controller is communicatively coupled with a storage medium and with a cache device and configured to interface with a processor or a memory of a computer system. The controller is further...
RE45086 Method and apparatus for prefetching recursive data structures  
Computer systems are typically designed with multiple levels of memory hierarchy. Prefetching has been employed to overcome the latency of fetching data or instructions from or to memory....
8806135 Load store unit with load miss result buffer  
A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored...
8806142 Anticipatory response pre-caching  
Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or...
8806140 Dynamic memory module switching with read prefetch caching  
A system and method are provided for using a system-on-chip (SoC) memory manager to optimize the use of off-chip memory modules. A SoC memory controller receives a request for a first data block,...
8806141 List based prefetch  
A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current...
8806145 Methods and apparatuses for improving speculation success in processors  
Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality...
8799580 Storage apparatus and data processing method  
To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or...
8799554 Methods and system for swapping memory in a virtual machine environment  
In this disclosure, techniques are described for more efficiently sharing resources across multiple virtual machine instances. For example, techniques are disclosed for allowing additional virtual...
8788759 Double-buffered data storage to reduce prefetch generation stalls  
A prefetch unit includes a program prefetch address generator that receives memory read requests and in response to addresses associated with the memory read request generates prefetch addresses...
8775742 System and method for cache management in a DIF enabled storage system  
A system and method for caching file data is disclosed. In one embodiment, in a method for caching file data stored in a storage device, wherein the file data is used by an application running on...
8775741 Using temporal access patterns for determining prefetch suitability  
A storage control system includes a prefetch controller that identifies memory regions for prefetching according to temporal memory access patterns. The memory access patterns identify a number of...
8775716 Methods and systems for defragmenting virtual machine prefetch data on physical storage  
A computer-implemented method for defragmenting virtual machine prefetch data. The method may include obtaining prefetch information associated with prefetch data of a virtual machine. The method...
8776034 Dynamically maintaining coherency within live ranges of direct buffers  
Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a...
8762650 Prefetching tracks using multiple caches  
Provided are a computer program product, sequential access storage device, and method for managing data in a sequential access storage device receiving read requests and write requests from a...
8762649 Bounding box prefetcher  
A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing...
8749569 Information processing apparatus, information processing method, and program  
There is provided an information processing apparatus including a storage unit for storing a transition frequency database storing transition frequency information representing a frequency of a...
8745212 Access to network content  
A method and system for improving access to network content are described. Aspects of the disclosure minimize the delay between a navigation event and a network response by prerendering the next...
8745158 Application-guided bandwidth-managed caching  
Methods and systems for populating a cache memory that services a media composition system. Caching priorities are based on a state of the media composition system, such as media currently within...
8738861 Data prefetching method for distributed hash table DHT storage system, node, and system  
Embodiments of the present disclosure provide a data prefetching method, a node, and a system. The method includes: a first storage node receives a read request sent by a client, determines a...
8732413 Method and system for preloading page using control flow  
A method and system for page preloading using a control flow are provided. The method includes extracting preload page information from one or more pages in a first program code, and generating a...
8732405 Method of reducing response time for delivery of vehicle telematics services  
A method of operating a predictive data cache includes receiving a request for telematics service from a telematics service requester, determining the subject matter of the request, querying a...
8732355 Dynamic data prefetching  
Technology is disclosed for data prefetching on a computing device utilizing a cloud based file system. The technology can receive a current execution state and a data access pattern associated...
8732406 Mechanism for determining read-ahead length in a storage system  
A storage system tracks statistical behavior of client read requests directed to a storage device to form prediction about data that the client will require next. The storage system collects the...
8725988 Pre-fetching data into a memory  
Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or...
8719510 Bounding box prefetcher with reduced warm-up penalty on memory block crossings  
A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines...
8719593 Secure processing device with keystream cache and related methods  
A secure processing device may include an external memory storing encrypted data, and a processor cooperating with the external memory. The processor is configured to generate address requests for...
8713261 Caching techniques  
Described are techniques for caching. At a first point in time, a first set of data portions currently stored in a first cache of a first data storage system is determined. Each data portion of...
8713260 Adaptive block pre-fetching method and system  
A method and system may include fetching a first pre-fetched data block having a first length greater than the length of a first requested data block, storing the first pre-fetched data block in a...