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7099999 Apparatus and method for pre-fetching data to cached memory using persistent historical page table data  
A computer system includes a main memory, at least one processor, and at least one level of cache. The system maintains reference history data with respect to each addressable page in memory,...
7099995 Metadata access during error handling routines  
A data storage control unit is coupled to one or more host devices and to one or more physical storage units. Data is stored in one of the storage units and, for data integrity, copied to another...
7093077 Method and apparatus for next-line prefetching from a predicted memory address  
A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory...
7093079 Snoop filter bypass  
Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may...
7089284 Method and system for client-side caching  
An improved method and system for client-side caching that transparently caches suitable network files for offline use. A cache mechanism in a network redirector transparently intercepts requests...
7089371 Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory  
A microprocessor apparatus for exclusive prefetch and initialization of cache lines, including translation logic and execution logic. The translation logic translates a block allocate and...
7089369 Method for optimizing utilization of a double-data-rate-SDRAM memory system  
A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described....
7089370 Apparatus and method for pre-fetching page data using segment table data  
A computer system includes a main memory, at least one processor, and at least one level of cache. The system contains at least one segment table having multiple segment entries recording the...
7089368 Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory  
A microprocessor apparatus for exclusive prefetch of a block of data from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended block...
7089367 Reducing memory access latencies from a bus using pre-fetching and caching  
The present invention is a method and apparatus to reduce latency in accessing a memory from a bus. The apparatus comprises a pre-fetcher and a cache controller. The pre-fetcher pre-fetches a...
7086063 System and method for file caching in a distributed program build environment  
A method is described comprising: scheduling jobs for a program build to execute in parallel across a plurality of nodes; predicting the files required to complete each of the jobs; and preloading...
7082499 External memory control device regularly reading ahead data from external memory for storage in cache memory, and data driven type information processing apparatus including the same  
When the cache memory unit reads the last word of a page of the cache memory, the external memory interface reads ahead data of a prescribed number of pages ahead of the relevant page. Thus, data...
7080209 Method and apparatus for processing a load-lock instruction using a relaxed lock protocol  
A processing core using a lock scoreboard mechanism is provided. The lock scoreboard is adapted to manage a load-lock instruction. The load-lock scoreboard includes a plurality of scoreboard...
7080210 Microprocessor apparatus and method for exclusive prefetch of a cache line from memory  
A microprocessor apparatus that enables exclusive prefetch of a cache line from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended...
7080212 Closed loop adaptive prestage method, system, and product for prestaging cache blocks  
A method, system, and computer program product are disclosed for dynamically determining and adjusting a number of data blocks to be prestaged in a cache included in the storage device. The...
7076613 Cache line pre-load and pre-own based on cache coherence speculation  
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor...
7073030 Method and apparatus providing non level one information caching using prefetch to increase a hit ratio  
A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1...
7062608 Storage device adapter equipped with integrated cache  
When streaming data is sent to a client, server capabilities are restricted by the ability to retrieve data from a storage unit, the data transfer rate drops and processing time increases. A...
7058767 Adaptive memory access speculation  
A method and system for speculatively pre-fetching data from a memory. A memory controller on a data bus “snoops” data requests put on the data bus by a bus control logic. Based on information in...
7055005 Methods and apparatus used to retrieve data from memory into a RAM controller before such data is requested  
A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The RAM controller may store such data into a prefetch buffer.
7055016 Computer system including a memory controller configured to perform pre-fetch operations  
A computer system including a memory controller configured to perform pre-fetch operations. A computer system includes a first system memory, a second system memory and a first and a second memory...
7051177 Method for measuring memory latency in a hierarchical memory system  
A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads...
7051162 Methods and apparatus used to retrieve data from memory before such data is requested  
A memory controller retrieves data from memory before such data has actually been requested by an electrical device. The memory controller may store such data into a prefetch buffer.
7051159 Method and system for cache data fetch operations  
A cache controller structure and method are provided for managing cache access for a computer system. The computer system has a processor having a direction flag and configured to run a repetitive...
7043608 Methods and apparatus to manage a cache memory  
Methods and apparatus to manage a cache memory. An example method of managing a cache comprises identifying program states associated with an executing program; comparing a time of first discovery...
7039747 Selective smart discards with prefetchable and controlled-prefetchable address space  
A bridging device has a first port to allow the device to communicate with other devices on an expansion bus and a second port to allow the device to communicate with devices on a second bus. The...
7039766 Prescheduling sequential data prefetches in a preexisting LRU cache  
A shared system memory, such as a cache, buffers Input/Output (I/O) requests between one or more host computers and one or more data storage servers or devices. The cache may be configured to...
7035979 Method and apparatus for optimizing cache hit ratio in non L1 caches  
A method and apparatus for increasing the performance of a computing system and increasing the hit ratio in at least one non-L1 cache. A caching assistant and a processor are embedded in a...
7035980 Effects of prefetching on I/O requests in an information processing system  
A data look-ahead control is provided to realize a high cache hit rate and improves responsiveness in an information processing system. In the data look-ahead control, when it is determined that...
7032097 Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache  
A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on...
7028142 System and method for reducing access latency to shared program memory  
System and method for reducing access latency to a shared program memory. The program memory is shared by more than one processor. The system includes fetch buffers (one per processor), prefetch...
7028160 Processing device with prefetch instructions having indicator bits specifying cache levels for prefetching  
An information processing system includes a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory two hierarchical...
7024663 Method and system for generating object code to facilitate predictive memory retrieval  
A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a...
7024465 Method for queued overlap transfer of files  
It is therefore an object of the invention to provide a system and method for prequeuing of files predicted to be desired by a user, through a telecommunications link, into a local cache, based on...
7020749 Signal processor, prefetch instruction method and prefetch instruction program  
A signal processor including a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory and an external memory...
7017010 Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length  
The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated...
7016349 Logic for generating multicast/unicast address (es)  
An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the...
7000081 Write back and invalidate mechanism for multiple cache lines  
A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation...
7000077 Device/host coordinated prefetching storage system  
A system including a data requester and a storage system. The storage system determines which prefetch data to include with demand data, without the data requester specifying the prefetch data,...
6996639 Configurably prefetching head-of-queue from ring buffers  
A method includes providing a prefetch cache of entries corresponding to communication rings stored in memory, the communication rings to store information passed from at least one first...
6996680 Data prefetching method  
A prefetching program preliminarily executes acquisition of SQL statements which are executed repeatedly and an analysis of a content of such processing so as to grasp data to be fetched in...
6996674 Method and apparatus for a global cache directory in a storage cluster  
A method, apparatus, and article of manufacture provide the ability to maintain cache in a clustered environment. The cache is maintained in both a primary and secondary node. When data is...
6993630 Data pre-fetch system and method for a cache memory  
A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache....
6993629 Prestaging data into cache in preparation for data transfer operations  
Disclosed is a method, system, and program for prestaging data into cache from a storage system in preparation for data transfer operations. A first processing unit communicates data transfer...
6993586 User intention modeling for web navigation  
The disclosed subject matter models or predicts a user's intention during network or WWW navigation. Specifically, a statistical multi-step n-gram probability model is used to predict a user's...
6988169 Cache for large-object real-time latency elimination  
A system and method for reducing data transfer latency and network-induced jitter in computer networks that can handle the transfer of large object data types such as multimedia objects without...
6986000 Interleaving apparatus and deinterleaving apparatus  
A signal record reproduction device 1 of the invention comprises a microcomputer 12 and a memory 17. A series of data blocks are divided into a plurality of items of element data. The element data...
6983356 High performance memory device-state aware chipset prefetcher  
A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the...
6981017 Predictive pre-download using normalized network object identifiers  
The invention provides a method for predicting which network objects are likely to be requested by a web user from a web server, such as that used in conjunction with an internetworking...
6981099 Smart-prefetch  
A method and system for the smart prefetching of instructions is disclosed. The method includes computing an effective memory latency of a request for data and using the effective memory latency...