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7234025 Microprocessor with repeat prefetch instruction  
A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction....
7231495 Speculative data streaming disk drive and system  
A disk drive capable of supporting speculative data transfers. Requested first data are read from the disk drive. Before the first data are read, a determination is made as to whether there are...
7231496 Method, system and program product for caching data objects  
Under the present invention, a history of requests for data objects are tracked and maintained in a cache log. Based on the history, certain data objects are prefetched into a cache. When a...
7231494 Storage and retrieval system for WEB cache  
The invention provides a storage and retrieval routine for Web objects. A Web page typically includes several objects such as text, images and hyper-links to other Web pages. Each Web page and its...
7228387 Apparatus and method for an adaptive multiple line prefetcher  
A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a...
7225297 Compressed cache lines incorporating embedded prefetch history data  
An apparatus and method utilize compressed cache lines that incorporate embedded prefetch history data associated with such cache lines. In particular, by compressing at least a portion of the...
7225299 Supporting speculative modification in a data cache  
Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator...
7225318 Dynamic prefetch in continuous burst read operation  
In a continuous burst memory read operation, a dynamic prefetch circuit compares a prefetched address with a received address. If the compared addresses are identical, the prefetched address is...
7222219 Memory control method and memory control apparatus for pipeline processing  
A signal generator detects a stage in which a central processing unit (CPU) reads an interrupt vector number from an instruction controller based on an address on an address bus and generates an...
7216203 Read ahead technique for network based file systems  
One embodiment of the present invention includes a method for enabling a client node to automatically read ahead data from a network based file system. Specifically, in response to an application...
7216202 Method and apparatus for supporting one or more servers on a single semiconductor chip  
One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to...
7206918 Address predicting apparatus and methods  
Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation...
7206902 System, apparatus and method for predicting accesses to a memory  
A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and...
7200719 Prefetch control in a data processing system  
In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit...
7194583 Controlling the replacement of prefetched descriptors in a cache  
A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send...
7194584 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Prefetch command control method, prefetch command control apparatus and cache memory control apparatus
 
A prefetch command control apparatus is provided. A protocol slot generation unit, when receiving from a CPU a prefetch command in which a utilization time of data to be prefetched is specified,...
7188215 Apparatus and method for renaming a cache line  
A microprocessor apparatus is provided that enables exclusive allocation and renaming a cache line. The apparatus includes translation logic and execution logic. The translation logic translates...
7181574 Server cluster using informed prefetching  
A method and apparatus that provides informed prefetching and enhanced memory utilization in a server cluster to improve failover and startup time of a resource group executed by a server cluster....
7181539 System and method for data synchronization  
Data is synchronized among multiple web servers, each of which is coupled to a common data server. Each web server retrieves a scheduled activation time from the data server. If the current time...
7174006 Method and system of VoiceXML interpreting  
A VoiceXML interpreting system and method including a VoiceXML Interpreter. The VoiceXML interpreter includes a Fetcher operative to retrieve documents, a compiler operative to compile documents...
7168070 Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer  
A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to...
7165146 Multiprocessing computer system employing capacity prefetching  
Various embodiments of a multiprocessing computer system employing capacity prefetching are disclosed. In one embodiment, a cache subsystem implements a method for prefetching data. The method...
7165148 Data prefetch method for indirect references  
To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead,...
7165147 Isolated ordered regions (IOR) prefetching and page replacement  
The concept of isolated ordered regions to maintain coordinates of nodes is used by associating each node with coordinates relative to a containing region. Modifications to nodes within a region...
7162609 Translation lookaside buffer prediction mechanism  
According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an...
7162588 Processor prefetch to match memory bus protocol characteristics  
Memory pages within a memory subsystem are typically accessed using an off chip memory controller coupled to an external bus. Data elements, in the form of a cache line, propagate along the...
7155575 Adaptive prefetch for irregular access patterns  
A computer program product determines whether a loop has a high usage count. If the computer program product determines the loop has a high usage count, the computer program product determines...
7155576 Pre-fetching and invalidating packet information in a cache memory  
A technique for managing a cache memory coupled to an intermediate node's processor. Packets acquired by the intermediate node that are destined for processing by the processor are tracked,...
7149850 Memory control apparatus executing prefetch instruction  
A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a...
7146467 Method of adaptive read cache pre-fetching to increase host read throughput  
Exemplary systems, methods, and devices employ receiving an operational parameter characteristic of a storage device, and adapting a read cache pre-fetch depth based in part on the operational...
7143242 Dynamic priority external transaction system  
A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.
7143243 Tag array access reduction in a cache memory  
A cache memory is disclosed with reduced tag array searches for sequential memory accesses. The cache memory has components such as at least one tag array, at least one data array associated with...
7143241 Cache management in a mobile device  
A user visiting a space is equipped with a mobile device in communication with a service system. Media items held by the service system are associated with various locations around the space and a...
7139784 Dead timestamp identification and elimination  
The performance of an application is improved by identifying and eliminating items with dead time-stamps and eliminating work on items with irrelevant time-stamps. An algorithm executing in each...
7139878 Method and apparatus for dynamic prefetch buffer configuration and replacement  
A memory controller and method thereof configures a prefetch buffer dynamically for interfacing between multiple bus masters of different burst support and multiple memories having different...
7139879 System and method of improving fault-based multi-page pre-fetches  
A system and method of improving fault-based multi-page pre-fetches are provided. When a request to read data randomly from a file is received, a determination is made as to whether previous data...
7133973 Arithmetic processor  
An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls...
7133969 System and method for handling exceptional instructions in a trace cache based processor  
A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace...
7130967 Method and system for supplier-based memory speculation in a memory subsystem of a data processing system  
A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs...
7124252 Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system  
An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the...
7124262 Selectivity pipelining and prefetching memory data  
A processor-based device (e.g., a wireless device) may include a processor and a semiconductor memory (e.g., a flash memory) to selectively pipeline and prefetch memory data, such as executable...
7120752 Multi-processor computer system with cache-flushing system using memory recall  
A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of...
7120751 Dynamic streaming buffer cache algorithm selection  
A streaming media cache comprises a mass storage device configured to store streaming media data, a cache memory coupled to the mass storage device, the cache memory configured to store a subset...
7120754 Synchronous DRAM with selectable internal prefetch size  
A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode...
7117309 Method of detecting sequential workloads to increase host read throughput  
Exemplary systems and methods analyze cache data to detect a sequential workload to facilitate pre-fetching effectiveness. An exemplary address analysis module for sequential workload detection...
7111126 Apparatus and method for loading data values  
An apparatus and method for loading data values from a memory system are provided. The data processing apparatus comprises a data processing unit operable to execute instructions, and a register...
7111125 Apparatus and method for renaming a data block within a cache  
A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic...
7107406 Method of prefetching reference objects using weight values of referrer objects  
In a client-cache-server system, the weight value of a first object which is maintained in the cache and linked to a second object maintained in the server is determined. Based on the weight...
7107401 Method and circuit to combine cache and delay line memory  
A method and a digital processor circuit to process digital delays are provided. The digital processor circuit may comprise circuit memory and a processor module such as a digital signal processor...
7103724 Method and apparatus to generate cache data  
Briefly, in accordance with an embodiment of the invention, a method to generate cache data is provided, wherein the method includes identifying access data transmitted from a storage device...