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9043550 Adjustment of the number of task control blocks allocated for discard scans  
A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform...
9037803 Randomized page weights for optimizing buffer pool page reuse  
In general, the disclosure is directed to techniques for choosing which pages to evict from the buffer pool to make room for caching additional pages in the context of a database table scan. A...
9032158 Method, system and apparatus for identifying a cache line  
A method of identifying a cache line of a cache memory (180) for replacement, is disclosed. Each cache line in the cache memory has a stored sequence number and a stored transaction data stream...
9026737 Enhancing memory buffering by using secondary storage  
A method is used in enhancing memory buffering by using secondary storage. A buffer cache pool is supplemented with a secondary storage. A portion of a volatile memory of a data storage system is...
9021208 Information processing device, memory management method, and computer-readable recording medium  
An information processing device includes a memory and a processor coupled to the memory, wherein the processor executes a process comprising selecting data included in a same file as deletion...
9015419 Avoiding aborts due to associativity conflicts in a transactional environment  
Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI)...
9003128 Cache system and processing apparatus  
According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the...
8990504 Storage controller cache page management  
A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory...
8977823 Store buffer for transactional memory  
Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a...
8977818 Combined transparent/non-transparent cache  
In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a...
8972664 Multilevel cache hierarchy for finding a cache line on a remote node  
Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests...
8966180 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8959289 Data cache block deallocate requests  
A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is...
8954674 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8930631 Efficient management of computer memory using memory page associations and memory  
A system and a computer program product manages memory operations in a data processing system. The system includes a processor executing instructions that causes the processor to read a first...
8930629 Data cache block deallocate requests in a multi-level cache hierarchy  
In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a...
8930630 Cache memory controller and method for replacing a cache block  
The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller...
8922565 System and method for using a secondary processor in a graphics system  
A system, method and apparatus are disclosed, in which a processing unit is configured to perform secondary processing on graphics pipeline data outside the graphics pipeline, with the output from...
8924359 Cooperative tiering  
Various systems and methods for cooperative tiering between an application and a storage device. One method can include receiving information from the application where the information identifies...
8918587 Multilevel cache hierarchy for finding a cache line on a remote node  
Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests...
8918602 Dynamically altering time to live values in a data cache  
A TTL value for a data object stored in-memory in a data grid is dynamically adjusted. A stale data tolerance policy is set. Low toleration for staleness would mean that eviction is certain, no...
8914574 Content addressable memory and method of searching data thereof  
The present invention discloses a content addressable memory and a method of searching data thereof. The method includes generating a hash index data item from a received input data item;...
8914582 Systems and methods for pinning content in cache  
An application server maintains a first plurality of applications in non-volatile memory. The application server loads into volatile memory a subset of the first plurality of applications. The...
8904111 Cache memory with CAM and SRAM sub-tags and generation control  
A cache memory includes a CAM with an associativity of n (where n is a natural number) and an SRAM, and storing or reading out corresponding data when a tag address is specified by a CPU connected...
8880652 Heuristic browser predictive pre-caching  
A method and computer readable medium are disclosed for predictive caching of web pages for display through a screen of a mobile computing device. A load request is received at a mobile computing...
8874852 Data cache block deallocate requests in a multi-level cache hierarchy  
In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a...
8868842 Memory system, method of controlling memory system, and information processing apparatus  
A WC resource usage is compared with an auto flush (AU) threshold Caf that is smaller than an upper limit Clmt, and when the WC resource usage exceeds the AF threshold Caf, the organizing state of...
8862827 Efficient multi-level software cache using SIMD vector permute functionality  
A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used...
8856455 Data cache block deallocate requests  
A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is...
8849351 Vacating low usage packet data sessions in a wireless communication system  
The present invention provides a method involving at least one mobile unit having at least one first session with a base station router. The method includes vacating at least one first session...
8843706 Memory management among levels of cache in a memory hierarchy  
Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main...
8838903 Priority ordered multi-medium solid-state storage system and methods for use  
A hierarchical data-storage system has a volatile storage medium, a first non-volatile storage medium, and a controller including a ranking engine tracking data writes to each of the memory...
8825944 Populating strides of tracks to demote from a first cache to a second cache  
Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks...
8806139 Cache set replacement order based on temporal set recording  
A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a...
8806137 Cache replacement using active cache line counters  
An apparatus for performing data caching comprises at least one cache memory including multiple cache lines arranged into multiple segments, each segment having a subset of the cache lines...
8799578 Managing unmodified tracks maintained in both a first cache and a second cache  
Provided are a computer program product, system, and method for managing unmodified tracks maintained in both a first cache and a second cache. The first cache has unmodified tracks in the storage...
8799580 Storage apparatus and data processing method  
To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or...
8793436 Cache management of tracks in a first cache and a second cache for a storage  
Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks...
8793555 Method of controlling a semiconductor storage device  
A method of controlling a nonvolatile semiconductor memory includes checking, at a first interval period, an error count of data stored in a first group, the first group including a plurality of...
8788758 Least profitability used caching scheme  
A storage proxy loads cache lines with data from a storage device. Storage access requests are received from an initiator and directed to the storage device. The storage proxy provides the data...
8782143 Disk management  
Systems, methods, and computer-program products store file segments by receiving a first file segment, and storing the first file segment in a first memory area having a highest ranking. The first...
8751750 Cache device, data management method, program, and cache system  
A deleted cache determining part determines a cache data which is to be deleted from a data storing part in a case where a sum of a data amount of a data which is recorded to the data storing part...
8751745 Method for concurrent flush of L1 and L2 caches  
The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a...
8745332 Cache management of tracks in a first cache and a second cache for a storage  
Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks...
8745334 Sectored cache replacement algorithm for reducing memory writebacks  
An improved sectored cache replacement algorithm is implemented via a method and computer program product. The method and computer program product select a cache sector among a plurality of cache...
8732404 Method and apparatus for managing buffer cache to perform page replacement by using reference time information regarding time at which page is referred to  
A method and apparatus manages a buffer cache. An extended buffer is used to perform a page replacement algorithm using reference time information regarding a time at which a page is referred....
8719494 Management of partial data segments in dual cache systems  
For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data...
8713259 Method and apparatus for reacquiring lines in a cache  
A method and apparatus for controlling re-acquiring lines of memory in a cache is provided. The method comprises storing at least one atomic instruction in a queue in response to the atomic...
8700854 Managing unmodified tracks maintained in both a first cache and a second cache  
Provided are a computer program product, system, and method for managing unmodified tracks maintained in both a first cache and a second cache. The first cache has unmodified tracks in the storage...
8694728 Efficient online construction of miss rate curves  
Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient...