Matches 201 - 250 out of 253 < 1 2 3 4 5 6 >
Match Document Document Title
6119205 Speculative cache line write backs to avoid hotspots  
A cache system including a data cache memory comprising a plurality of cache lines. A tag store has an entry representing each line in the cache memory where each entry comprises tag information...
6115793 Mapping logical cache indexes to physical cache indexes to reduce thrashing and increase cache size  
A cache memory system which minimizes the latency and latency uncertainty of data memory access by allocating spare cache memories to subsequent conflicting requests, and maintaining the prior...
6105115 Method and apparatus for managing a memory array  
A NRU algorithm is used to track lines in each region of a memory array such that the corresponding NRU bits are reset on a region-by-region basis. That is, the NRU bits of one region are reset...
6105109 System speed loading of a writable cache code array  
SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache...
6098152 Method and apparatus for miss sequence cache block replacement utilizing a most recently used state  
A method and apparatus are provided for miss sequence cache block replacement in a cache including a plurality of cache blocks in a computer system. First checking for an invalid block is...
6098153 Method and a system for determining an appropriate amount of data to cache  
A method and a system for determining how much data to cache, that is, optimizing disk caching control by selecting the optimal staging mode are disclosed. Specifically, the method and system of...
6092159 Implementation of configurable on-chip fast memory using the data cache RAM  
A write-through data cache which incorporates a line addressable locking mechanism. By executing a software lock instruction or unlock instruction, a microprocessor controls the locking or...
6088767 Fileserver buffer manager based on file access operation statistics  
Fileserver buffers are managed so as to improve the hit ratio for read accesses to the fileserver by clients by grouping related files into filesets, collecting fileserver access operation (i.e.,...
6047358 Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups  
A computer system, a cache memory and a process, each enabling a cache replacement policy with locking. The computer system comprises a processing device and a memory system, the memory system...
6047362 Delayed removal of address mapping for terminated processes  
An application binary interface includes linkage structures for interfacing a binary application program to a digital computer. Virtual address spaces are allocated for processes respectively. Page...
6014728 Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations  
A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to...
6012126 System and method for caching objects of non-uniform size using multiple LRU stacks partitions into a range of sizes  
A system and method for caching objects of non-uniform size. A caching logic includes a selection logic and an admission control logic. The admission control logic determines whether an object not...
6006033 Method and system for reordering the instructions of a computer program to optimize its execution  
A system and method are provided that allows the results of an instruction trace mechanism to globally restructure the instructions. The process reorders the instructions in an executable program,...
5983313 EDRAM having a dynamically-sized cache memory and associated method  
The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main...
5974507 Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm  
A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides"...
5913225 Cache flush mechanism for a secondary cache memory  
An effective mechanism for cache flushing that can be applied to a memory system operated in dual-mode is disclosed. The dual-mode is composed of two modes using two physically distinguished main...
5909695 Maximal concurrent lookup cache for computing systems having a multi-threaded environment  
A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry being identified by an entry number....
5897655 System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference  
In a method and system for storing information within a set of a cache memory, the set has multiple locations. The information is stored at a selected one of the locations. The selected location...
5893139 Data storage device and storage method in which algorithms are provided for calculating access frequencies of data  
A plurality of data storage media which are constructed in a hierarchical structure of a plurality of levels having different access times and have different access information items are provided,...
5881266 Priority-based memory management method and apparatus  
The hit ratio of a cache memory in a data base processing system is improved by changing the priority of erasing cache data. A forward/backward pointer and a backward/forward pointer are contained...
5875465 Cache control circuit having a pseudo random address generator  
A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache...
5873100 Internet browser that includes an enhanced cache for user-controlled document retention  
A browser for requesting and receiving documents from a network includes a cache which stores a plurality of documents and has a user-defined storage limit. At least one of the plurality of...
5860102 Cache memory circuit  
A cache memory circuit 36 is described which has a separate read bus 90 and write bus 98. When a given cache row is selected, then simultaneous read and write operations can take place to different...
5850534 Method and apparatus for reducing cache snooping overhead in a multilevel cache system  
A memory system for reducing cache snooping overhead for a multilevel cache system has a highest cache level connected to a main memory and a lowest cache level connected to a processor or other...
5838946 Method and apparatus for accomplishing processor read of selected information through a cache memory  
The present invention provides for a method and apparatus for reading non-cachable information in a cache memory system. The cache memory system includes a processor, a buffer, a multiplexor, main...
5835972 Method and apparatus for optimization of data writes  
An improved method for performing memory writes from a processor in a personal computer system is provided whereby single writes are combined into burst writes based on detection of suitable write...
5822759 Cache system  
A cache memory system maintains an ordered linked list of cache items having scores that are positively correlated with frequencies of access and negatively correlated with a size that is...
5815703 Computer-based uniform data interface (UDI) method and system using an application programming interface (API)  
A computer-based uniform data interface (UDI) system for accessing in a uniform manner data from a data source with an arbitrary organization. The UDI system provides a UDI application programming...
5805787 Disk based disk cache interfacing system and method  
Large numbers of relatively small (e.g., 1.8" or smaller) off-the-shelf disk drives are controlled to maximize the highest throughput performance at the least cost between a host computer and a...
5787471 Cache memory management apparatus having a replacement method based on the total data retrieval time and the data size  
In a cache memory management device, a time measuring unit measures a time period required to obtain data from a database. The data obtained from the database is linked to the time information and...
5787473 Cache management system using time stamping for replacement queue  
A shared system memory buffers data transfers between a plurality of host computers and a plurality of data storage devices. The system memory includes a cache memory and a number of queues and...
5787472 Disk caching system for selectively providing interval caching or segment caching of vided data  
A system and method for caching sequential data streams in a cache storage device. For each information stream, a determination is made as to whether its data blocks should discarded from cache as...
5778432 Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register  
A method and apparatus for efficiently performing a cache operation in a processor (70) for both flushing and non-flushing. One embodiment uses a cache flush control bit (100) in a data cache (90)...
5774685 Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative conditions  
The computer processing unit of the present invention includes a new prefetch instruction, referred to as an STOUCH instruction, which provides the capability to encode compile-time speculations...
5765196 System and method for servicing copyback requests in a multiprocessor system with a shared memory  
In a multiprocessor system having a shared memory, each central processor services copyback requests from other central processors. Each central processor has a writeback buffer along with a...
5737752 Cache replacement mechanism  
An n-way set-associative cache (where n is an integer greater than 1), includes a replacement mechanism for selecting a cache line for replacement. Each cache line has an associated priority tag...
5734861 Log-structured disk array with garbage collection regrouping of tracks to preserve seek affinity  
A log-structured array (LSA) includes a relatively large, non-volatile cache memory as well as a memory segment write buffer. The LSA cache memory contains both updated logical tracks received from...
5729712 Smart fill system for multiple cache network  
An optimization system for the cache-fill operation in a multi-set cache memory operates to select that cache-set which indicates it has invalid data therein and/or also indicates that an...
5703787 Wave analyzing apparatus and wave analyzing method  
A wave analyzing apparatus and method reduce the amount of time required for wave analysis. When changing wave data of a specified discrete point within an analysis domain expressed by a plurality...
5619675 Method and apparatus for cache memory management using a two level scheme including a bit mapped cache buffer history table and circular cache buffer list  
The cache buffer management system functions in a mass storage subsystem to locate a less recently referenced cache buffer to be overwritten with new data. The system of the present invention...
5615353 Method for operating a cache memory using a LRU table and access flags  
A computer data storage device made up of both solid state storage and rotating magnetic disk which maintains a fast response time approaching that of a solid state device for many workloads and...
5603045 Microprocessor system having instruction cache with reserved branch target section  
A Harvard architecture data processing system includes a processor, main memory, an instruction cache, and a data cache. As is generally known with the Harvard architecture, these components are...
5584014 Apparatus and method to preserve data in a set associative memory device  
An apparatus and method to dynamically partition a set-associative memory device is described. The apparatus includes a set identification device to specify a group of set-associative data blocks...
5581726 Control system for controlling cache storage unit by using a non-volatile memory  
A control system controls a disk unit and a cache storage unit having a cache memory and a nonvolatile memory based on a writing instruction supplied from a host computer. The control system...
5553266 Update vs. invalidate policy for a snoopy bus protocol  
The present invention is directed to a computer apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus. The bus is...
5551002 System for controlling a write cache and merging adjacent data blocks for write operations  
A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at...
5526511 Enhanced least recently used round robin cache management method and apparatus for allocation and destaging of cache segments  
The disclosure relates to a cache management method for a post-store cache. Recently referenced units of storage in the cache are identified and a round robin cache replacement method is generally...
5497477 System and method for replacing a data entry in a cache memory  
A method and apparatus called a cache insertion selector for selecting a slot of a memory cache in which to insert data. The access history of a slot is monitored with a single boolean variable...
5493669 Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits  
A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one...
5450565 Circuit and method for selecting a set in a set associative cache  
A set select circuit and method for selecting a set in a set associative cache in a microprocessor. The set select circuit, responsive to a main clock, includes an input latch coupled to receive...
Matches 201 - 250 out of 253 < 1 2 3 4 5 6 >