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7606977 |
Context save and restore with a stack-based memory structure
A multi-threaded processor adapted to couple to external memory comprises a controller and data storage operated by the controller. The data storage comprises a first portion and a second portion,...
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7596665 |
Mechanism for a processor to use locking cache as part of system memory
The present invention provides a mechanism for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or...
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7596664 |
Collapsed distributed cooperative memory for interactive and scalable media-on-demand systems
This invention treats of a two-level cache management method for continuous media files of a proxy server. In the first level, the method reserves collapsed buffers in the cache for every active...
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7590802 |
Direct deposit using locking cache
The present invention provides a mechanism of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main...
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7584327 |
Method and system for proximity caching in a multiple-core system
Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as...
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7581066 |
Cache isolation model
One embodiment of the invention employs techniques for providing isolation for exclusivity of operation. Isolation may exist between different application and/or different threads or virtual...
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7577854 |
Information storage device having a divided area in memory area
An information storage apparatus capable of setting the number and sizes of partitioned areas resulting from partitioning a memory area based on a user's intention is provided. For this purpose, an...
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7565492 |
Method and apparatus for preventing software side channel attacks
A method for managing a cache is disclosed. A context switch is identified. It is determined whether an application running after the context switch requires protection. Upon determining that the...
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7565490 |
Out of order graphics L2 cache
Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that...
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7562190 |
Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture
A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability...
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7558937 |
Disk array device memory having areas dynamically adjustable in size
A disk array device having a plurality of hard disk units has a large-capacity memory mounted on a controller module which controls the whole device. The large-capacity memory has a system area...
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7558919 |
Dynamic cache partitioning
Described are techniques for determining a cache slot. A set of criteria for each of a plurality of families is received. A received data operation associated with a first of said plurality of...
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7555611 |
Memory management of local variables upon a change of context
A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java...
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7552284 |
Least frequently used eviction implementation
Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an...
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7549022 |
Avoiding cache line sharing in virtual machines
Avoiding cache-line sharing in virtual machines can be implemented in a system running a host and multiple guest operating systems. The host facilitates hardware access by a guest operating system...
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7546426 |
Storage having a logical partitioning capability and systems which include the storage
A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file...
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7546422 |
Method and apparatus for the synchronization of distributed caches
A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol...
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7543042 |
Remote access method for accessing dynacache data
A method for accessing an internal dynamic cache of a Websphere-type Application Server (WAS) from an external component that includes the step of establishing a software interface component within...
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7539820 |
Disk device and control method for cache
Embodiments of the invention allow cache control optimized for the processing characteristics of application programs, and thus improve data transfer efficiency. In one embodiment, a disk device...
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7536692 |
Thread-based engine cache partitioning
In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled...
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7536510 |
Hierarchical MRU policy for data cache
A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each...
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7529891 |
Balanced prefetching exploiting structured data
Balanced prefetching automatically balances the benefits of prefetching data that has not been accessed recently against the benefits of caching recently accessed data, and can be applied to most...
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7526608 |
Methods and apparatus for providing a software implemented cache memory
Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory...
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7523262 |
Apparatus and method for providing global session persistence
An apparatus and method provide persistent data during a user session on a networked computer system. A global data cache is divided into three sections: trusted, protected, and unprotected. An...
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7512951 |
Method and apparatus for time-sliced and multi-threaded data processing in a communication system
A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to...
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7509440 |
Programmable controller and communication unit therefor
A programmable controller includes a CPU unit, a communication unit and peripheral units connected together through an internal bus. The communication unit has a bus master function, including a...
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7500058 |
Cache memory managing method for computer system
A computer system acquires mapping information of data storage regions in respective layers from a layer of DBMSs to a layer of storage subsystems, grasps correspondence between DB data and storage...
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7493607 |
Statically speculative compilation and execution
A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the...
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7490200 |
L2 cache controller with slice directory and unified cache structure
A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a...
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7484047 |
Apparatus and method for composing a cache memory of a wireless terminal having a coprocessor
A terminal apparatus and method for controlling access by a processor and coprocessor to data buses that connect memories. The apparatus and method comprise a first flash memory connected to a...
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7484043 |
Multiprocessor system with dynamic cache coherency regions
A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency...
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7478218 |
Adaptive cache sizing based on monitoring of regenerated and replaced cache entries
A runtime code manipulation system is provided that supports code transformations on a program while it executes. The runtime code manipulation system uses code caching technology to provide...
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7475194 |
Apparatus for aging data in a cache
A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier...
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7475190 |
Direct access of cache lock set data without backing memory
Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a...
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7469318 |
System bus structure for large L2 cache array topology with different latency domains
A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock...
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7467280 |
Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring...
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7464223 |
Storage system including storage adapters, a monitoring computer and external storage
A storage system having a cluster configuration that prevents a load from concentrating on a certain storage node and enhances access performance is disclosed. The storage system is provided with...
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7457922 |
Cache line placement prediction for multiprocessor non-uniform cache architecture systems
In a multiprocessor non-uniform cache architecture system, multiple CPU cores shares one non-uniform cache that can be partitioned into multiple cache portions with varying access latencies. A...
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7454580 |
Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations
A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for...
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7454571 |
Heuristic cache tuning
In some embodiments, a computer system comprises a cache configured to cache data. The computer system is configured to monitor the cache and data that is potentially cacheable in the cache to...
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7451248 |
Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The...
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7447843 |
Storage system with independently adjustable cache memory partitions
An object of the present invention is to provide a storage system which is shared by a plurality of application programs, wherein optimum performance tuning for a cache memory can be performed for...
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7437514 |
Cache system
A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the...
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7437513 |
Cache memory with the number of operated ways being changed according to access pattern
An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with...
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7437512 |
Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the...
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7434247 |
System and method for determining the desirability of video programming events using keyword matching
The desirability of programming events may be determined using metadata for programming events that includes goodness of fit scores associated with categories of a classification hierarchy one or...
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7434001 |
Method of accessing cache memory for parallel processing processors
A method of accessing cache memory for parallel processing processors includes providing a processor and a lower level memory unit. The processor utilizes multiple instruction processing members...
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7428616 |
Method and apparatus for appending buffer areas to requested memory
An information processing apparatus has a CPU, a memory, a cache memory and a cache controller. When an acquisition of an area of a prescribed size is requested in the memory, a size equivalent to...
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7415575 |
Shared cache with client-specific replacement policy
A cache shared by multiple clients implements a client specific policy for replacing entries in the event of a cache miss. A request from any client can hit any entry in the cache. For purposes of...
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7392347 |
Systems and methods for buffering data between a coherency cache controller and memory
In one embodiment, the present invention is directed to a system processing memory transaction requests. The system includes a controller for storing and retrieving cache lines and a buffer...
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