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7624234 |
Directory caches, and methods for operation thereof
A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into...
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7617366 |
Method and apparatus for filtering snoop requests using mulitiple snoop caches
A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have...
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7617364 |
System, method and storage medium for prefetching via memory block tags
A method and system for memory management are provided. The system includes a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of...
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7613884 |
Multiprocessor system and method ensuring coherency between a main memory and a cache memory
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a...
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7606974 |
Automatic caching generation in network applications
Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads...
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7600080 |
Avoiding deadlocks in a multiprocessor system
In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a...
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7596663 |
Identifying a cache way of a cache access request using information from the microtag and from the micro TLB
A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor;...
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7594079 |
Data cache virtual hint way prediction, and applications thereof
A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way...
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7590792 |
Cache memory analyzing method
It is done to read information containing an address of a memory at which a cache miss is generated, from a cache memory. The numbers of cache misses generated at each cache miss generated address...
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7587556 |
Store buffer capable of maintaining associated cache information
A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer...
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7584326 |
Method and system for maximum residency replacement of cache memory
Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag miss allocation. Herein,...
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7580675 |
Data communication apparatus functioning as ID tag and ID-tag reader and writer
A data communication apparatus includes an antenna, an analog front-end circuit, and a controller. The analog front-end circuit is connected between the antenna and the controller and includes...
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7574572 |
Cache memory, system, and method of storing data
A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data...
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7574564 |
Replacement pointer control for set associative cache and method
A set associative cache includes a plurality of sets, where each set has a plurality of ways. The set associative cache has a plurality of replacement pointers where each set of the plurality of...
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7573880 |
Set-associative memory architecture for routing tables
A set-associative architecture (IPStash) restricts routing table prefixes to a limited number of lengths using a controlled, prefix-expansion technique. Since this inflates the routing tables,...
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7571282 |
Computer system having a flash memory storage device
A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads,...
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7565491 |
Associative matrix methods, systems and computer program products using bit plane representations of selected segments
Associative matrix compression methods, systems, computer program products and data structures compress an association matrix that contains counts that indicate associations among pairs of...
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7562191 |
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way...
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7558921 |
Method for data set replacement in 4-way or greater locking cache
A method and means are provided for increasing both the MMBR (minimum misses before replaceable) and MHBR (minimum hits before replaceable) parameters for a virtual 3-way cache, consisting of three...
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7546417 |
Method and system for reducing cache tag bits
A method of accessing data from a cache is disclosed. Tag bits of data among sets and ways of cache lines are divided into common subtags and remaining subtags. Similarly, an access address tag is...
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7543113 |
Cache memory system and method capable of adaptively accommodating various memory line sizes
A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to...
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7542968 |
Attribute data management system
Cache hit ratio is improved in a cache apparatus that reads and caches contents from a large-scale database. The cache apparatus includes a cache section for recording a plurality of sets. Each set...
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7536510 |
Hierarchical MRU policy for data cache
A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each...
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7533219 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way...
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7529889 |
Data processing apparatus and method for performing a cache lookup in an energy efficient manner
A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing...
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7526628 |
Optimizing cache efficiency within application software
The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and...
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7526610 |
Sectored cache memory
A memory cache comprising, a data sector having a sector ID, wherein the data sector stores a data entry, a primary directory having a primary directory entry, wherein a position of the primary...
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7526609 |
Runtime register allocator
Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure...
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7526608 |
Methods and apparatus for providing a software implemented cache memory
Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory...
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7516275 |
Pseudo-LRU virtual counter for a locking cache
A computer implemented method and system for managing replacement of sets in a locked cache. A cache access by a program is performed, and a side of a binary tree pointed to by a base leaf is...
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7502889 |
Home node aware replacement policy for caches in a multiprocessor system
A home node aware replacement policy for a cache chooses to evict lines which belong to local memory over lines which belong to remote memory, reducing the average transaction cost of incorrect...
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7502887 |
N-way set associative cache memory and control method thereof
The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way...
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7493448 |
Prevention of conflicting cache hits without an attendant increase in hardware
A multiprocessor system includes a plurality of processors that share a multiple-way set-associative cache memory that includes a directory and a data array, the multiprocessor system being...
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7475192 |
Cache organization for power optimized memory access
An N-set associative cache organization is disclosed. The cache organization comprises a plurality of SRAMs, wherein the data within the SRAMs such that a first 1/N of a plurality of cache lines is...
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7475190 |
Direct access of cache lock set data without backing memory
Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a...
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7472230 |
Preemptive write back controller
A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The...
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7472226 |
Methods involving memory caches
A method for accessing data in memory comprising, receiving address bits associated with a data item including a first tag, an index, and a sector ID from a requestor, associating the index with a...
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7467260 |
Method and apparatus to purge remote node cache lines to support hot node replace in a computing system
An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second...
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7461211 |
System, apparatus and method for generating nonsequential predictions to access a memory
A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a...
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7461208 |
Circuitry and method for accessing an associative cache with parallel determination of data and data availability
A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache....
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7457917 |
Reducing power consumption in a sequential cache
In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data...
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7451271 |
Physically-tagged cache with virtually-tagged fill buffers
A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.
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7437513 |
Cache memory with the number of operated ways being changed according to access pattern
An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with...
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7430642 |
System and method for unified cache access using sequential instruction information
Techniques for accessing a unified cache to obtain instruction information are provided. One exemplary technique includes accessing, during a first instruction access, a first cache line of a first...
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7418583 |
Data dependency detection using history table of entry number hashed from memory address
A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least...
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7406569 |
Instruction cache way prediction for jump targets
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
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7397683 |
Associative memory having a mask function for use in a network router
When one or more storage data are coincident with single search data ( 12 ), an associative memory ( 1 ) carries out logical sum for all of storage data with a valid state for storage data as true....
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7395373 |
Set-associative cache using cache line decay counts and set overflow
Embodiments of a method for reducing conflict misses in a set-associative cache by mapping each memory address to a primary set and at least one overflow set are described. If a conflict miss...
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7395372 |
Method and system for providing cache set selection which is power optimized
A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data...
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7392349 |
Table management within a policy-based routing system
A method of controlling a content addressable memory (CAM) device. A data structure is generated that specifies (i) a prioritized set of rules and (ii) storage locations within the CAM device for...
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