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9003127 Storing data in a system memory for a subsequent cache flush  
Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where...
8990504 Storage controller cache page management  
A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory...
8990507 Storing data in a system memory for a subsequent cache flush  
Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where...
8990505 Cache memory bank selection  
Devices, systems, methods, and other embodiments associated with a cache memory are described. In one embodiment, a cache tag array includes tag banks. The cache memory further includes a bank...
8984227 Advanced coarse-grained cache power management  
Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other...
8977818 Combined transparent/non-transparent cache  
In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a...
8972659 Memory control device, memory device, memory control method, and program  
There is provided a memory control device including a device driver that executes writing or reading of data to/from a main storage unit and temporary writing or reading of data to/from a cache...
8972665 Cache set selective power up  
Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch...
8966180 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8966182 Software and hardware managed dual rule bank cache for use in a pattern matching accelerator  
A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using...
8954674 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8953354 Semiconductor memory device and method of driving semiconductor memory device  
A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural...
8949530 Dynamic index selection in a hardware cache  
Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A...
8938586 Memory system with flush processing from volatile memory to nonvolatile memory utilizing management tables and different management units  
A memory system includes: a cache memory, a nonvolatile semiconductor memory, and a controller. The controller includes a plurality of management tables that manage data stored in the cache memory...
8924649 Persistent cacheable high volume manufacturing (HVM) initialization code  
A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a...
8924653 Transactional cache memory system  
A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an...
8914574 Content addressable memory and method of searching data thereof  
The present invention discloses a content addressable memory and a method of searching data thereof. The method includes generating a hash index data item from a received input data item;...
8914580 Reducing cache power consumption for sequential accesses  
In some embodiments, a cache may include a tag array and a data array, as well as circuitry that detects whether accesses to the cache are sequential (e.g., occupying the same cache line). For...
8909872 Computer system with coherent interconnection  
A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is...
8904111 Cache memory with CAM and SRAM sub-tags and generation control  
A cache memory includes a CAM with an associativity of n (where n is a natural number) and an SRAM, and storing or reading out corresponding data when a tag address is specified by a CPU connected...
8904112 Method and apparatus for saving power by efficiently disabling ways for a set-associative cache  
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and...
8874849 Sectored cache with a tag structure capable of tracking sectors of data stored for a particular cache way  
Technologies are generally described for a system for copying particular data in a particular sector of a particular block from a memory into a cache, in some examples, the cache includes a tag...
8868835 Cache control apparatus, and cache control method  
A cache control apparatus according to the present invention includes a cache allocation control unit which allocates each of a plurality of ways included in a cache memory to one or more of tasks...
8868844 System and method for a software managed cache in a multiprocessing environment  
A method for implementing a software-managed cache comprises determining an object identifier (ID) for each of a first set of objects of a plurality of objects resident in a local memory, to...
8862827 Efficient multi-level software cache using SIMD vector permute functionality  
A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used...
8856448 Methods and apparatus for low intrusion snoop invalidation  
Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a...
8850112 Non-volatile hard disk drive cache system and method  
A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The...
8839025 Systems and methods for retiring and unretiring cache lines  
The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation...
8832378 System and a method for selecting a cache way  
A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being...
8825955 Data processing apparatus having a cache configured to perform tag lookup and data access in parallel, and a method of operating the data processing apparatus  
A data processing apparatus has a cache with a data array and a tag array. The tag array stores address tag portions associated with the data values in the data array. The cache performs a tag...
8812783 Operation apparatus, cache apparatus, and control method thereof  
An apparatus comprising first holding units each of which includes first nodes connected in series and shifts first data in each first node in a first direction, second holding units each of which...
8812786 Dual-granularity state tracking for directory-based cache coherence  
A system and method of providing directory cache coherence are disclosed. The system and method may include tracking the coherence state of at least one cache block contained within a region using...
8806174 Method and system for hash key memory footprint reduction  
A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a...
8775740 System and method for high performance, power efficient store buffer forwarding  
The present disclosure describes a system and method for high performance, power efficient store buffer forwarding. Some illustrative embodiments may include a system, comprising: a processor...
8769204 Programmable cache access protocol to optimize power consumption and performance  
A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring...
8756375 Non-volatile cache  
Apparatuses, systems, and methods are disclosed for caching data. A method includes directly mapping a logical address of a backing store to a logical address of a non-volatile cache. A method...
8736627 Systems and methods for providing a shared buffer in a multiple FIFO environment  
Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial...
8719500 Technique for tracking shared data in a multi-core processor or multi-processor system  
A technique to track shared information in a multi-core processor or multi-processor system. In one embodiment, core identification information (“core IDs”) are used to track shared information...
8719509 Cache implementing multiple replacement policies  
In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in...
8700855 System and method for supporting a tiered cache  
A computer-implemented method and system can support a tiered cache, which includes a first cache and a second cache. The first cache operates to receive a request to at least one of update and...
8683465 Virtual image deployment with a warm cache  
A cache image including only cache entries with valid durations of at least a configured deployment date for a virtual machine image is prepared via an application server for the virtual machine...
8656107 On-demand allocation of cache memory for use as a preset buffer  
A data processing system comprises data processing circuitry, a cache memory, and memory access circuitry. The memory access circuitry is operative to assign a memory address region to be...
8656112 Checkpointed tag prefetcher  
A dual-mode prefetch system for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags identifying the data stored in the...
8656108 Method and apparatus for saving power by efficiently disabling ways for a set-associative cache  
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and...
8645629 Persistent cacheable high volume manufacturing (HVM) initialization code  
A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a...
8639885 Reducing implementation costs of communicating cache invalidation information in a multicore processor  
A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache...
8635408 Controlling power of a cache based on predicting the instruction cache way for high power applications  
A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code....
8631207 Cache memory power reduction techniques  
Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache...
8631206 Way-selecting translation lookaside buffer  
Set-associative caches having corresponding methods and computer programs comprise: a data cache to provide a plurality of cache lines based on a set index of a virtual address, wherein each of...
8583872 Cache memory having sector function  
A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to...