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6647457 Content addressable memory having prioritization of unoccupied entries  
According to one embodiment, a content addressable memory (CAM) (100) can include a number of CAM entries (102-0 to 102-n) and corresponding status stores (106-0 and 106-n). Match indications from...
6643739 Cache way prediction based on instruction base register  
A way prediction scheme for a partitioned cache is based on the contents of instructions that use indirect addressing to access data items in memory. The contents of indirect-address instructions...
6643738 Data processor utilizing set-associative cache memory for stream and non-stream memory addresses  
A data processor has a cache memory with an associative memory for storing at least a first and second groups of associations between a respective main memory addresses and cache memory locations....
6643737 Cache lock device and method therefor  
A cache lock device eliminates the need of transferring data to a cache at execution of a lock instruction by excluding the possibility of an invalid data to be locked in the cache. The cache lock...
6640286 Cache control system  
A cache memory unit that preferentially stores specific lines at the cache memory, according to the program nature, dynamically changes the priority ranks of lines, and increases the cache memory...
6640283 Apparatus for cache compression engine for data compression of on-chip caches to increase effective cache size  
A compression engine for a cache memory subsystem has a pointer into cache tag memory and cache data memory and an interface coupled to the pointer and capable of being coupled to cache tag...
6631445 Cache structure for storing variable length data  
A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single...
6629207 Method for loading instructions or data into a locked way of a cache memory  
Methods of operating an instruction cache memory in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having...
6622213 Two-way cache system and method for interfacing a memory unit with a peripheral device using first and second cache data regions  
A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit....
6622209 Use of non-count data and index hashing to reduce false hits in a non-tagged, n-way cache  
In one embodiment of the invention, data values which are provided to a non-tagged, n-way cache are written into the cache in a non-count form. Whereas a counter tends to quickly saturate to one...
6622208 System and methods using a system-on-a-chip with soft cache  
A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in...
6622211 Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty  
A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the...
6608793 Efficient management method of memory cell array  
The present invention relates to a method of efficiently managing a memory cell array. A new memory cell array management method of the present invention allows reduction of power consumption and...
6604174 Performance based system and method for dynamic allocation of a unified multiport cache  
The present invention provides a performance based system and method for dynamic allocation of a unified multiport cache. A multiport cache system is disclosed that allows multiple single-cycle...
6601155 Hot way caches: an energy saving technique for high performance caches  
A device is presented including a processor. A local memory is connected to the processor. The processor includes a hot way cache accessing process. A method is presented that includes accessing a...
6598147 Data processing device and method  
The present invention has for its object to provide a data processing apparatus which improves the point that in data processing employing an associative storage device, performing the high speed...
6594728 Cache memory with dual-way arrays and multiplexed parallel output  
A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense...
6591347 Dynamic replacement technique in a shared cache  
A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by...
6591343 Predecode in parallel with TLB compare  
An apparatus and method are provided for determining initial information about a macro instruction prior to decoding of the macro instruction by translation logic within a pipeline microprocessor....
6587923 Dual line size cache directory  
In a computer system having a processor, a memory system including multiple levels of caches L1, L2, . . . , Ln−1 and including main memory Ln, and in which the cache Li−1 includes lines of size s...
6584547 Shared cache structure for temporal and non-temporal instructions  
A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for...
6581140 Method and apparatus for improving access time in set-associative cache systems  
A system provides a method and apparatus for accessing information in a cache in a data processing system. The system optimizes a speed-critical path within the cache system by using a prediction...
6581139 Set-associative cache memory having asymmetric latency among sets  
A set-associative cache memory having asymmetric latency among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets...
6567952 Method and apparatus for set associative cache tag error detection  
An apparatus includes a plurality of error detection circuits. Each of the plurality of error detection circuits is coupled to one of a like plurality of ways in a set associative cache memory to...
6560677 Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory  
Ways of a cache memory system are designated as being in one of three subsets: a normal subset, a transient subset, and a locked subset. The designation of the respective subsets is provided by a...
6560679 Method and apparatus for reducing power consumption by skipping second accesses to previously accessed cache lines  
A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory....
6560676 Cache memory system having a replace way limitation circuit and a processor  
A cache memory system employing a set associative system with a plurality of ways which can store data having a same set address is disclosed. The cache memory system includes a replace circuit...
6553477 Microprocessor and address translation method for microprocessor  
A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The...
6553473 Byte-wise tracking on write allocate  
An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The that apparatus and method...
6549983 Cache memory system and method for managing the same  
A cache memory system reduces the rate of cache misses. The cache memory system includes a first auxiliary storage device which stores first information blocks and a second auxiliary storage...
6542963 Partial match partial output cache for computer arithmetic operations  
An arithmetic device having a cache for performing arithmetic operations is provided. The cache stores previously performed resultant data and operand for an arithmetic operation and upon...
6542965 Cache line replacement using cable status to bias way selection  
A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice...
6539458 Hierarchical memory for efficient data exchange control  
A data processing system and method involving a data requesting element and a first memory element from which said data requesting element requests data is described. An example of such a system...
6535959 Circuit and method for reducing power consumption in an instruction cache  
A circuit and method for reducing power in a memory, such as an instruction cache, having a number of blocks, are disclosed. A power reduction signal (also called a “same block” signal) is...
6516388 Method and apparatus for reducing cache pollution  
In a cache which writes new data over less recently used data, methods and apparatus which dispense with the convention of marking new cache data as most recently used. Instead, non-referenced...
6516399 Dynamically configurable page table  
The reliability and operability of semiconductor devices is improved using a circuit arrangement and method that improves the ability to manage data storage and retrieval. According to one example...
6516387 Set-associative cache having a configurable split and unified mode  
A set-associative cache having a selectively configurable split/unified mode. The cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the...
6513104 Byte-wise write allocate with retry tracking  
An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The apparatus and method allow...
6496903 Cache memory device  
A cache memory device by which a processing speed can be elevated and which comprises a primary cache memory containing two primary ways of WAY0 and WAY1 each retaining a bit LRU0 and a bit LRU1...
6493812 Apparatus and method for virtual address aliasing and multiple page size support in a computer system having a prevalidated cache  
A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support for various levels of address...
6493792 Mechanism for broadside reads of CAM structures  
A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted test value to the corresponding...
6490662 System and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module  
A computer system and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module includes placing a “lock” command on the...
6473835 Partition of on-chip memory buffer for cache  
A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the...
6470438 Methods and apparatus for reducing false hits in a non-tagged, n-way cache  
In one embodiment of the invention, each data value which is provided to a non-tagged, n-way cache is hashed with a number of bits which correspond to the data value, thereby producing a hashed...
6467025 Cache memory system and method utilizing doubly-linked loop of cache lines and a single pointer to address a cache line in the doubly-linked loop  
An improved cache memory and method of operation thereof. The cache memory includes a doubly-linked loop of cache lines and a single pointer operable to address a cache line in the doubly-linked...
6467019 Method for memory management in ternary content addressable memories (CAMs)  
According to one embodiment (300) a ternary CAM can include rules stored in CAM locations, where each rule includes match criteria. CAM locations determine priority among various rules. An input...
6460117 Set-associative cache memory having a mechanism for migrating a most recently used set  
A set-associative cache memory having a mechanism for migrating a most recently used set is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class...
6460127 Apparatus and method for signal processing  
An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including...
6460118 Set-associative cache memory having incremental access latencies among sets  
A set-associative cache memory having incremental access latencies among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number...
6449694 Low power cache operation through the use of partial tag comparison  
A method for conserving power during a cache memory operation is disclosed. The validity and the parity of the tag address are checked. If the tag is invalid or the parity bit does not check, the...