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6871265 Method and apparatus for maintaining netflow statistics using an associative memory to identify and maintain netflows  
Methods and apparatus are disclosed for maintaining netflow statistics using an associative memory to identify and maintain netflows. A lookup operation is performed on a set of associative memory...
6868485 Computer system with integrated directory and processor cache  
A computer system with an integrated directory and processor cache. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than...
6868484 Replacement data error detector  
A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a...
6865646 Segmented distributed memory module cache  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6848025 Method and system for programmable replacement mechanism for caching devices  
A caching device using an N-way replacement mechanism is disclosed. The replacement mechanism comprises at least one replacement order list with N positions, with the first-to-replace position at...
6848028 Microprocessor having a page prefetch cache for database applications  
A microprocessor cache configuration for reducing database cache misses and improving the processing speed, comprising a level-1 data cache, and a page prefetch cache. The page prefetch cache is...
6848035 Semiconductor device with multi-bank DRAM and cache memory  
A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM...
6839807 Multi-way set associative cache memory  
A multi-way set associative cache memory includes a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables the sense amplifier to select...
6836828 Instruction cache apparatus and method capable of increasing a instruction hit rate and improving instruction access efficiency  
The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a...
6836826 Multilevel cache system and method having a merged tag array to store tags for multiple data arrays  
A multilevel cache system and method. A first data array and a second data array are coupled to a merged tag array. The merged tag array stores tags for both the first data array and second data...
6834328 Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures  
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management...
6832294 Interleaved n-way set-associative external cache  
An n-way interleaved set-associative external cache utilizes standard burst memory devices such as DDR (double data rate) memory devices. The interleaved set-associative cache organization scheme...
6823434 System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state  
The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries...
6823426 System and method of data replacement in cache ways  
Disclosed are a system and method of replacing data in cache ways of a cache memory array. If one or more cache ways are locked from replacement, a cache way may be selected from among the...
6804744 Content addressable memory having sections with independently configurable entry widths  
According to one embodiment, a content addressable memory (CAM) (100) includes a number of sections (106-1 to 106-i) having data value entries that can be compared to comparand values and/or...
6801207 Multimedia processor employing a shared CPU-graphics cache  
A highly integrated multimedia processor employs a shared cache between tightly coupled central processing and graphics units to provide the graphics unit access to data retrieved from system...
6799250 Cache control device  
A cache control device of the invention comprises a first register for holding address data, a second register for holding address data held by the first register at the next timing, caches for...
6792508 Cache with multiple fill modes  
A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache...
6792498 Memory system with mechanism for assisting a cache memory  
Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a...
6785772 Data prefetching apparatus in a data processing system and method therefor  
A data processing system (20) is able to perform parameter-selectable prefetch instructions to prefetch data for a cache (38). When attempting to be backward compatible with previously written...
6779102 Data processor capable of executing an instruction that makes a cache memory ineffective  
A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the...
6775748 Methods and apparatus for transferring cache block ownership  
Methods and apparatus for transferring cache block ownership from a first cache to a second cache without performing a writeback to a main memory are disclosed. Prior to the ownership transfer,...
6775752 System and method for efficiently updating a fully associative array  
The present invention relates to a mechanism for updating a fully associative array which is used to store entries associated with speculated instructions. Preferably, the array includes a...
6763422 Cache memory capable of reducing area occupied by data memory macro units  
A cache memory is provided which is capable of reducing areas occupied by data memory macro units and preventing delays in data transmission caused by wirings, thus improving performance of the...
6763431 Cache memory system having block replacement function  
A cache memory system includes a tag RAM storing tags in a plurality of sets thereof, a data RAM storing data in a plurality of sets corresponding to the tag RAM sets, and a control logic...
6754776 Method and system for logical partitioning of cache memory structures in a partitoned computer system  
A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The...
6754775 Method and apparatus for facilitating flow control during accesses to cache memory  
One embodiment of the present invention provides a system that facilitates flow control to support pipelined accesses to a cache memory. When an access to the cache memory generates a miss, the...
6751700 Date processor and storage system including a set associative cache with memory aliasing  
A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced...
6748484 Match resolution circuit for an associative memory  
A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data...
6748390 Associative memory device with optimized occupation, particularly for the recognition of words  
A memory device having an associative memory for the storage of data belonging to a plurality of classes. The associative memory has a plurality of memory locations aligned along rows and columns...
6745292 Apparatus and method for selectively allocating cache lines in a partitioned cache shared by multiprocessors  
A computer system includes a cache memory which is shared by multiple processors. The cache memory is divided into a plurality of regions. Each of the processor is exclusively associated with one...
6745291 High speed LRU line replacement system for cache memories  
An N-way set associative data cache system comprises a cache controller adapted to receive a request for data and instructions. The cache controller includes a cache buffer register for storing...
6745288 Staggering call stack offsets for multiple duplicate control threads  
When a new control thread is initialized in a multi-thread software program, it is determined whether a like control thread has previously been instantiated. If so, a stack offset for the new...
6742053 Two-dimensional execution queue for host adapters  
A two-dimensional hardware control block execution queue includes a plurality of initiator queues where each initiator queue includes at least one hardware control block. Each of the initiator...
6732238 Set-associative cache memory having variable time decay rewriting algorithm  
A set-associative structure replacement algorithm is particularly beneficial for irregular set-associative structures which may be affected by different access patterns, and different...
6724297 Multiple read method and system for a set of tags bearing distinct ID codes  
A method and device for reading a set of tags, each with an ID code, of N bits, wherein the identification of these codes is carried out successively, bit by bit, by scanning a binary search tree...
6725336 Dynamically allocated cache memory for a multi-processor unit  
The resources of a partitioned cache memory are dynamically allocated between two or more processors on a multi-processor unit (MPU). In one embodiment, the MPU includes first and second...
6718439 Cache memory and method of operation  
An N-way set associative virtual victim cache in which cache accesses are automatically directed only to the data array in the most recently used way. The cache memory comprises: 1) N ways, each...
6715035 Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency  
A cache for use in a memory controller, which processes data in a computer system having at least one processor, and a method for processing data utilizing a cache, are disclosed. The cache...
6711665 Associative processor  
An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated...
6694408 Scalable replacement method and system in a cache memory  
The invention provides a system and method for executing a replacement selection algorithm embedded in each associativity of a cache memory architecture. Each associativity in a cache has an...
6687790 Single bank associative cache  
A cache controller is intimately associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where it is sent to the...
6687789 Cache which provides partial tags from non-predicted ways to direct search if way prediction misses  
A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to...
6684297 Reverse directory for facilitating accesses involving a lower-level cache  
One embodiment of the present invention provides a multiprocessor system that includes a number of processors with higher-level caches that perform memory accesses through a lower-level cache....
6684298 Dynamic reconfigurable memory hierarchy  
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management...
6681312 Power saving address translation buffer  
In an address translation buffer, multiple content-addressable memories of a first memory array store previous process identifiers for comparing them with a new process identifier to produce a...
6681294 Cache control apparatus for a microprocessor  
A cache control apparatus for an information processing system having a cache memory with a plurality of ways is disclosed, in which the hardware amount is reduced and the delay of the response...
6681295 Fast lane prefetching  
A computer system has a set-associative, multi-way cache system, in which at least one way is designated as a fast lane, and remaining way(s) are designated slow lanes. Any data that needs to be...
6678792 Fast and accurate cache way selection  
A way-determination scheme for an n-way associative cache is provided that is based on the entirety of the line address of a requested data item, thereby eliminating the possibility of a...
6665775 Cache dynamically configured for simultaneous accesses by multiple computing engines  
A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first...