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7017009 Cache memory device  
A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when...
7013367 Caching associative memory using non-overlapping data  
An apparatus and method for caching data in an associative memory cache using a single non-overlapping entry, wherein the non-overlapping entry is created from a matching entry and one or more...
7007136 Storage device and cache memory device in set associative system  
A storage device in a set associative system includes N-pieces (N is an integer of 2 or larger) of ways each having a plurality of entries containing at least replace flags and predetermined data,...
7000076 Random generator  
A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a value within a second range. A...
6996675 Retrieval of all tag entries of cache locations for memory address and determining ECC based on same  
The retrieval of all tag entries of cache locations for a memory address is disclosed, as well as the determining of an error correcting code (ECC) for the tag entries based thereon. Tag entries...
6993622 Bit level programming interface in a content addressable memory  
An apparatus and method for generating a comparand in a content addressable memory array. The apparatus includes a content addressable memory (CAM) array and translation circuitry to receive...
6988164 Compare circuit and method for content addressable memory (CAM) device  
A content addressable memory (CAM) device (100) may include a number of sub-blocks (102-8 to 102-15) that can generate CAM search results. In a “search beyond” operation, sub-blocks (102-8 to...
6988168 Cache programmable to partition ways to agents and/or local/remote blocks  
A cache comprises a memory including a plurality of entries and a circuit. Each entry of the plurality of entries is configured to store a cache block. The circuit is configured to select a first...
6988167 Cache system with DMA capabilities and method for operating same  
In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data...
6986001 System and method for hierarchical approximation of least recently used replacement algorithms within a cache organized as two or more super-ways of memory blocks  
A system for approximating a least recently used (LRU) algorithm for memory replacement in a cache memory. In one system example, the cache memory comprises memory blocks allocated into sets of N...
6981096 Mapping and logic for combining L1 and L2 directories and/or arrays  
Architectures, methods and systems are presented which combine a multiple of directories (e. g. L1 and L2 directory) into a single directory, while still allowing the individual levels to use...
6976126 Accessing data values in a cache  
The present invention provides an apparatus and method for accessing data values in a cache and in particular accessing data values in an ‘n’ way set associative cache. A data processing apparatus...
6973557 Apparatus and method for dual access to a banked and pipelined data cache memory unit  
In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at...
6973540 Method and apparatus for selecting cache ways available for replacement  
In a multi-way cache, a method for selecting N ways available for replacement includes providing a plurality of rulesets where each one of the plurality of rulesets specifies N ways in the cache...
6968428 Microprocessor cache design initialization  
Techniques are disclosed for initializing a representation of a cache in a microprocessor design under test. The cache representation includes a plurality of cache entries, each of which is...
6965969 Non-uniform cache apparatus, systems, and methods  
An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of...
6961821 Reconfigurable cache controller for nonuniform memory access computer systems  
A method and structure for replacing cache lines in a computer system having a set associative cache memory is disclosed. The method establishes ranking guidelines utilizing a writable cache...
6961276 Random access memory having an adaptable latency  
A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for...
6961824 Deterministic setting of replacement policy in a cache  
A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the state of its replacement policy in...
6959363 Cache memory operation  
A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a...
6954827 Cache memory capable of selecting size thereof and processor chip having the same  
A multi-way set-associative cache memory is configured to operate only with those ways of the tag and data memories that operate normally, and excludes those ways of the tag and data memories that...
6954822 Techniques to map cache data to memory arrays  
Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks....
6954828 Management of caches in a data processing apparatus  
The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as...
6950906 System for and method of operating a cache  
A method of operating a cache comprises the steps of reading first information from a tag memory for at least two cache lines; reading second information from the tag memory for at least two cache...
6950902 Cache memory system  
A cache memory system having a small-capacity and high-speed access cache memory provided between a processor and a main memory, including a software cache controller for performing software...
6944711 Cache management method for storage device  
A cache management method disclosed herein enables optimal cache space settings to be provided on a storage device in a computer system where database management systems (DBMSs) run. Through the...
6944710 Multiple category CAM  
An apparatus and method is disclosed for a CAM match detection circuit with a multiple category CAM circuit. The multiple category CAM circuit provides category association tables to specify which...
6944714 Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache  
An embodiment of the invention provides a circuit and method for reducing power in multi-way set associative arrays. A control circuit detects when the next cache access will be taken from the...
6944713 Low power set associative cache  
A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.
6941421 Zero delay data cache effective address generation  
A method and system for accessing a specified cache line using previously decoded base address offset bits, stored with a register file, which eliminate the need to perform a full address decode...
6938126 Cache-line reuse-buffer  
A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch...
6938129 Distributed memory module cache  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6934798 CAM with policy based bandwidth allocation  
A content addressable memory (CAM) simultaneously searches packet categories in the CAM, and automatically allocates network resources, such as bandwidth, between the categories. Categories and...
6934811 Microprocessor having a low-power cache memory  
A cache is provided which has low power dissipation. An execution engine generates a sequential fetch signal indicating that data required at a next cycle is stored at a next location of just...
6931491 Hardware-assisted tuple space  
A hardware-assisted tuple space, comprising a tuple memory for storing tuples of key-value pairs of data; an anti-tuple memory for storing anti-tuples of key-value pairs of data; tuple attribute...
6931485 Disk array apparatus  
A cache memory comprises a group of cache pages which are normal data areas, and a group of work pages each for saving DIRTY data in an associated cache page. When write data transferred from a...
6931505 Distributed memory module cache command formatting  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6931493 Implementation of an LRU and MRU algorithm in a partitioned cache  
The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition...
6931490 Set address correlation address predictors for long memory latencies  
Set address correlation correlates between addresses belonging to a common address set. Addresses are grouped into address sets and correlations are created between addresses by set. The...
6925534 Distributed memory module cache prefetch  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6912628 N-way set-associative external cache with standard DDR memory devices  
A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes...
6901483 Prioritizing and locking removed and subsequently reloaded cache lines  
A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special...
6901476 Variable key type search engine and method therefor  
A system and method for storing arranged data in a memory, and for extracting the data therefrom, the system including: (a) a random access memory (RAM) including: (i) a first array of cells, the...
6898671 Data processor for reducing set-associative cache energy via selective way prediction  
The data processor has a set-associative cache memory capable of performing associative operation using tag information for an indexed cache line. The cache memory includes way prediction part for...
6889291 Method and apparatus for cache replacement for a multiple variable-way associative cache  
A method and apparatus for cache replacement in a multiple variable-way associative cache is disclosed. The method according to the present techniques partitions a cache array dynamically based...
6880044 Distributed memory module cache tag look-up  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6877067 Shared cache memory replacement control method and apparatus  
In a multiprocessor system in which a plurality of processors share an n-way set-associative cache memory, a plurality of ways of the cache memory are divided into groups, one group for each...
6874058 Content addressed memories  
A content addressable memory comprises a CAM control logic unit and plural cells connected in a chain. Each cell comprises a memory block coupled to a common address bus, a comparator coupled to a...
6874057 Method and apparatus for cache space allocation  
A method and apparatus are disclosed for allocating a section of a cache memory to one or more tasks. A set index value that identifies a corresponding set in the cache memory is transformed to a...
6874056 Method and apparatus for reducing cache thrashing  
A method and apparatus are disclosed for adaptively decreasing cache trashing in a cache memory device. Cache performance is improved by automatically detecting thrashing of a set and then...