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7330935 Set associative cache system and control method for cache memories  
A cache system comprises i (e.g., 2) groups of m (e.g., 2) ways and n (e.g., 2) sets of cache arrays, a set address decoder, a comparator, a cache address and cache management information. The set...
7330934 Cache memory with reduced power and increased memory bandwidth  
A digital processor with a cache that provides fast and low power operation. The cache contains a tag array and a data array. The tag array indicates whether a value is stored in the cache for a...
7318222 Methods for execution control acquistion of a program and for executing an optimized version of a program  
In a method for execution control acquisition of a program, during the execution of the program, it is determined when a hardware performance counter has reached a threshold. When the threshold is...
7310706 Random cache line refill  
A microprocessor includes random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and...
7308536 System bus read data transfers with data ordering control bits  
A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to...
7307861 Content addressable memory (CAM) cell bit line architecture  
A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also...
7308537 Half-good mode for large L2 cache array topology with different latency domains  
A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes...
7305521 Methods, circuits, and systems for utilizing idle time in dynamic frequency scaling cache memories  
Dynamic Frequency Scaling (DFS) cache memories that can be accessed during an idle time in a single low frequency DFS clock cycle are disclosed. The access can begin during the idle time in the...
7302524 Adaptive thread ID cache mechanism for autonomic performance tuning  
An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits...
7298637 Multiple match detection circuit and method  
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit...
7290081 Apparatus and method for implementing a ROM patch using a lockable cache  
A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first...
7290089 Executing cache instructions in an increased latency mode  
For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle...
7284094 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class  
A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch...
7259765 Head/data scheduling in 3D graphics  
A system for processing graphics data for a stream of graphics primitives, such as triangles. The system has a plurality of memories each for storing an index of the primitive. A controller...
7257672 Error protection for lookup operations performed on ternary content-addressable memory entries  
Lookup operations are performed on ternary content-addressable memory (TCAM) entries, with error protection provided. Groups of TCAM entries are programmed such that each of its entries differ by...
7246202 Cache controller, cache control method, and computer system  
In a computer system that concurrently executes a plurality of tasks, a cache controller eliminates the possibility of the hit rate of one task dropping due to execution of another task. A region...
7237067 Managing a multi-way associative cache  
Methods for storing replacement data in a multi-way associative cache are disclosed. One method comprises logically dividing the cache's cache sets into segments of at least one cache way;...
7228386 Programmably disabling one or more cache entries  
A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be...
7219184 Method and apparatus for longest prefix matching in processing a forwarding information database  
A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each...
7219195 Associative memory with invert result capability  
An associative memory with an invert result capability to allow the identification of an entry as being matched when an entry or portion thereof is specifically not matched is disclosed (or...
7213101 Classless interdomain routing using binary content addressable memory having mask bits and mask valid bits  
A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) Address processing. A binary CAM array is segmented into a plurality of array groups, each of...
7203797 Memory management of local variables  
A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local...
7200712 Associative memory system, network device, and network system  
This invention needs no priority encoder to connect the plural number of associative memories. The primary searching associative memory 4 of the associative memory 204 produces the intermediate...
7181572 Cache updating method and apparatus  
A method of updating a cache in an integrated circuit comprising: the cache; a processor connected to the cache via a cache bus; a memory interface connected to the cache via a first bus and to...
7177986 Direct access mode for a cache  
A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may...
7177983 Managing dirty evicts from a cache  
In a Constant Access Time Bounded (CATB) cache, if a dirty line in a search group of the cache is selected for eviction from the cache, marking the dirty line as evicted, selecting a replacement...
7143240 System and method for providing a cost-adaptive cache  
A cost-adaptive cache including the ability to dynamically maximize performance in a caching system by preferentially caching data according to the cost of replacing data. The cost adaptive cache...
7143239 Cache structure and methodology  
A cache structure comprising a plurality of tag arrays and a plurality of data arrays, the tag arrays each configured to point to lines of data in multiple ones of the plurality of data arrays,...
7136984 Low power cache architecture  
In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the...
7136967 Multi-level cache having overlapping congruence groups of associativity sets in different cache levels  
A computer cache memory having at least two levels includes associativity sets allocated to congruence groups, each congruence group having multiple associativity sets (preferably two) in the...
7127571 Method and system to adjust non-volatile cache associativity  
A method and system to adjust a non-volatile cache associativity are described. In one embodiment, the method and system include determining a status of the system; and setting an associativity...
7124249 Method and apparatus for implementing a software cache  
A method and apparatus for use in a computer system including a plurality of host computers including a root host computer and at least one child host computer. The root host computer exports at...
7120745 Cache memory device and memory allocation method  
A cache memory device comprises a secondary tag RAM that partially constitutes a secondary cache memory and employs a set associative scheme having a plurality of ways, and a secondary cache...
7114054 Systems and methods for increasing transaction entries in a hardware queue  
Systems and methods for increasing transaction entries in a hardware queue of the type having a fixed number of storage elements. One of a plurality of transaction entries in one of the storage...
7111124 Set partitioning for cache memories  
A method, apparatus, and signal-bearing medium for improving the performance of a cache when request streams with different spatial and/or temporal properties access the cache. A set in the cache...
7107408 Methods and apparatus for speculative probing with early completion and early request  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller...
7107409 Methods and apparatus for speculative probing at a request cluster  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A cache coherence controller...
7096318 Content-addressable (associative) memory devices  
A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel...
7093075 Location-based placement algorithms for set associative cache memory  
A system and method for reducing latency in memory systems is provided. A copy way is established in a set of a set associative cache, which is physically closer to a requesting entity than other...
7089396 Method and profiling cache for management of virtual memory  
A method and profiling cache for management of virtual memory includes a set of entries stored in the profiling cache. Each entry of the set of entries includes a page address, a time stamp for...
7085896 Method and apparatus which implements a multi-ported LRU in a multiple-clock system  
An apparatus for implementing a least-recently used (LRU) mechanism in a multi-port cache memory includes an LRU array and a shift decoder. The LRU array has multiple entries. The shift decoder...
7080213 System and method for reducing shared memory write overhead in multiprocessor systems  
A system and method for reducing shared memory write overhead in multiprocessor system. In one embodiment, a multiprocessing system implements a method comprising storing an indication of obtained...
7076613 Cache line pre-load and pre-own based on cache coherence speculation  
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor...
7069386 Associative memory device  
An associative memory support for a data processing system includes an associative memory device containing n-cells. A controller is provided for issuing an instruction to the associative memory...
7069388 Cache memory data replacement strategy  
A method for caching specified data in an n-way set associative memory with a copy-back update policy consists of the following steps. First, a row of the associative memory, organized as a...
7062607 Filtering basic instruction segments in a processor front-end for power conservation  
Power conservation may be achieved in a front end system by disabling a segment builder unless program flow indicates a sufficient likelihood of segment reuse. Power normally spent in collecting...
7047362 Cache system and method for controlling the cache system comprising direct-mapped cache and fully-associative buffer  
A method is provided for controlling a cache system. The cache system to be controlled comprises a direct-mapped cache configured with a small block size, and a fully associative spatial buffer...
7047363 Cache memory and control method thereof  
A cache memory related to the present invention is a cache memory employing a set associative system, for generating a valid bit for showing the presence of validity of a cache data, and comprises...
7035978 Method, system, and program for policies for improving throughput in remote mirroring systems  
Disclosed is a method, system, and program for determining which data to remove from storage. A first policy is used to determine when to remove a block of data of a first type. A second policy is...
7024536 Translation look-aside buffer for improving performance and reducing power consumption of a memory and memory management method using the same  
A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a...