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7571282 Computer system having a flash memory storage device  
A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads,...
7565491 Associative matrix methods, systems and computer program products using bit plane representations of selected segments  
Associative matrix compression methods, systems, computer program products and data structures compress an association matrix that contains counts that indicate associations among pairs of...
7562191 Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme  
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way...
7558921 Method for data set replacement in 4-way or greater locking cache  
A method and means are provided for increasing both the MMBR (minimum misses before replaceable) and MHBR (minimum hits before replaceable) parameters for a virtual 3-way cache, consisting of...
7546417 Method and system for reducing cache tag bits  
A method of accessing data from a cache is disclosed. Tag bits of data among sets and ways of cache lines are divided into common subtags and remaining subtags. Similarly, an access address tag is...
7542968 Attribute data management system  
Cache hit ratio is improved in a cache apparatus that reads and caches contents from a large-scale database. The cache apparatus includes a cache section for recording a plurality of sets. Each...
7543113 Cache memory system and method capable of adaptively accommodating various memory line sizes  
A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to...
7536510 Hierarchical MRU policy for data cache  
A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each...
7533219 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
 
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way...
7529889 Data processing apparatus and method for performing a cache lookup in an energy efficient manner  
A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing...
7526609 Runtime register allocator  
Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure...
7526608 Methods and apparatus for providing a software implemented cache memory  
Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory...
7526610 Sectored cache memory  
A memory cache comprising, a data sector having a sector ID, wherein the data sector stores a data entry, a primary directory having a primary directory entry, wherein a position of the primary...
7516275 Pseudo-LRU virtual counter for a locking cache  
A computer implemented method and system for managing replacement of sets in a locked cache. A cache access by a program is performed, and a side of a binary tree pointed to by a base leaf is...
7502889 Home node aware replacement policy for caches in a multiprocessor system  
A home node aware replacement policy for a cache chooses to evict lines which belong to local memory over lines which belong to remote memory, reducing the average transaction cost of incorrect...
7502887 N-way set associative cache memory and control method thereof  
The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the...
7493448 Prevention of conflicting cache hits without an attendant increase in hardware  
A multiprocessor system includes a plurality of processors that share a multiple-way set-associative cache memory that includes a directory and a data array, the multiprocessor system being...
7475192 Cache organization for power optimized memory access  
An N-set associative cache organization is disclosed. The cache organization comprises a plurality of SRAMs, wherein the data within the SRAMs such that a first 1/N of a plurality of cache lines...
7475190 Direct access of cache lock set data without backing memory  
Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in...
7472230 Preemptive write back controller  
A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The...
7472226 Methods involving memory caches  
A method for accessing data in memory comprising, receiving address bits associated with a data item including a first tag, an index, and a sector ID from a requestor, associating the index with a...
7467260 Method and apparatus to purge remote node cache lines to support hot node replace in a computing system  
An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second...
7461208 Circuitry and method for accessing an associative cache with parallel determination of data and data availability  
A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache....
7461211 System, apparatus and method for generating nonsequential predictions to access a memory  
A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as...
7457917 Reducing power consumption in a sequential cache  
In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data...
7451271 Physically-tagged cache with virtually-tagged fill buffers  
A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.
7437513 Cache memory with the number of operated ways being changed according to access pattern  
An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with...
7430642 System and method for unified cache access using sequential instruction information  
Techniques for accessing a unified cache to obtain instruction information are provided. One exemplary technique includes accessing, during a first instruction access, a first cache line of a...
7418583 Data dependency detection using history table of entry number hashed from memory address  
A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least...
7406569 Instruction cache way prediction for jump targets  
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
7397683 Associative memory having a mask function for use in a network router  
When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true....
7395372 Method and system for providing cache set selection which is power optimized  
A system and method for accessing a data cache having at least two ways for storing data at the same addresses. A first and second tag memory store first and second sets of tags identifying data...
7395373 Set-associative cache using cache line decay counts and set overflow  
Embodiments of a method for reducing conflict misses in a set-associative cache by mapping each memory address to a primary set and at least one overflow set are described. If a conflict miss...
7392349 Table management within a policy-based routing system  
A method of controlling a content addressable memory (CAM) device. A data structure is generated that specifies (i) a prioritized set of rules and (ii) storage locations within the CAM device for...
7392346 Memory updater using a control array to defer memory operations  
A memory having multiple locations for data storage is updated by performing the following method. The memory locations are grouped into commonly accessible groups of one or more data locations....
7389387 Distributed memory module cache writeback  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
7386658 Memory post-write page closing apparatus and method  
Apparatus and method to receive new requests for write transactions; compare rank, bank and page of new requests to those already stored and assemble chains of write commands directed to the same...
7386701 Prefetching hints  
A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for...
7386671 Smart cache  
A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache...
7376791 Memory access systems and methods for configuring ways as cache or directly addressable memory  
A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable...
7370154 Method and apparatus for maintaining coherence information in multi-cache systems  
A method and apparatus for maintaining coherence information in multi-cache systems is described herein. In one embodiment, the apparatus includes an Ingrained Sharing Directory Cache (ISDC) to...
7370151 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache  
A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working...
7366819 Fast unaligned cache access system and method  
A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple...
7360023 Method and system for reducing power consumption in a cache memory  
A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the...
7360041 Method for priority scheduling and priority dispatching of store conditional operations in a store queue  
A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each...
7353337 Reducing cache effects of certain code pieces  
Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since the...
7350016 High speed DRAM cache architecture  
A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an...
7337372 Method and apparatus for detecting multi-hit errors in a cache  
Multi-hit errors in a processor cache are detected by a multi-hit detection circuit coupled to the hit lines of the cache. The multi-hit detection circuit compares pairs of hit signals on the hit...
7336517 Physical priority encoder  
A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative...
7330936 System and method for power efficient memory caching  
A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address...