Match Document Document Title
7856576 Method and system for managing memory transactions for memory repair  
In one embodiment, a controller for an associative memory having n ways contains circuitry for sending a request to search an indexed location in each of the n ways for a tag, wherein the tag and...
7856532 Cache logic, data processing apparatus including cache logic, and a method of operating cache logic  
Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in...
7844778 Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements  
A method for replacing cached data is disclosed. The method in one aspect associates an importance value to each block of data in the cache. When a new entry needs to be stored in the cache, a...
RE41958 Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures  
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management...
7836256 Method and apparatus for application-specific dynamic cache placement  
One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and...
7827356 System and method of using an N-way cache  
A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list...
7827372 Intergrated circuit and a method of cache remapping  
An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted...
7818502 Selectively powering down tag or data memories in a cache based on overall cache hit rate and per set tag hit rate  
A CPU incorporating a cache memory is provided, in which a high processing speed and low power consumption are realized at the same time. A CPU incorporating an associative cache memory including...
7818645 Built-in self-test emulator  
Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a...
7809980 Error detector in a cache memory using configurable way redundancy  
A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as...
7809890 Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries  
Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a...
7805576 Information processing system, information processing board, and method of updating cache tag and snoop tag  
In an information processing system loaded with a CPU having cache and a system controller having a copy of a tag of the cache (snoop tag), and the CPU not issuing replacement information about...
7802077 Trace indexing via trace end addresses  
A new class traces for a processing engine, called “extended blocks,” possess an architecture that permits possible many entry points but only a single exit point. These extended blocks may be...
7788642 Displaying cache information using mark-up techniques  
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from...
7769954 Data processing system and method for processing data  
A data processing system includes: a cache memory comprising a plurality of ways, each of which stores a data line including a data and address information of the data; an analysis module that...
7765242 Methods and apparatus for structure layout optimization for multi-threaded programs  
A computer-implemented method for performing structure layout optimization of a data structure in a multi-threaded environment is provided. The method includes determining a set of code...
7761661 Physically-tagged cache with virtual fill buffers  
A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.
7761665 Handling of cache accesses in a data processing apparatus  
The present invention provides a data processing apparatus and method for handling cache accesses. The data processing apparatus comprises a processing unit operable to issue a series of access...
7743200 Instruction cache using perfect hash function  
In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect...
7739451 Method and apparatus for stacked address, bus to memory data transfer  
A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller...
7725656 Braided set associative caching techniques  
A method and apparatus for storing and retrieving data in an N-way set associative cache with N data array banks is disclosed. On a cache fill corresponding to a particular way, a portion of each...
7707358 Dual access for single port cache  
A method and system for accessing a single port multi-way cache with way dedication includes address multiplexers that simultaneously addresses a set of data and a set of program instructions in...
7698506 Partial tag offloading for storage server victim cache  
A technique for partially offloading, from a main cache in a storage server, the storage of cache tags for data blocks in a victim cache of the storage server, is described. The technique includes...
7698509 Snooping-based cache-coherence filter for a point-to-point connected multiprocessing node  
A multiprocessing node has a plurality of point-to-point connected microprocessors. Each of the microprocessors is also point-to-point connected to a filter. In response to a local cache miss, a...
7694075 System for enabling and disabling cache and a method thereof  
A second cache (e.g., L2 cache) is enabled or disabled based at least in part on an utilization of a first cache (e.g., L1 cache). The utilization of the first cache may be interpreted as an...
7693883 Online data volume deletion  
A system to delete a data volume may include storage of a plurality of data pages of the data volume of a data area into a cache, prevention of writing of data pages to the data volume, and...
7689772 Power-performance modulation in caches using a smart least recently used scheme  
The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a...
7676632 Partial cache way locking  
Systems and methods are disclosed for locking code in cache. A processor comprises a cache and a cache controller. The cache is configured to store a temporary copy of code residing in main...
7673102 Method and system for maximum residency replacement of cache memory  
Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag-miss allocation. Herein,...
7673101 Re-assigning cache line ways  
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from...
7657708 Methods for reducing data cache access power in a processor using way selection bits  
Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way...
7653790 Methods and apparatus for responding to a request cluster  
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors...
7650465 Micro tag array having way selection bits for reducing data cache access power  
Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register,...
7644234 Information processing apparatus with a cache memory and information processing method  
A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main...
7636811 Cache memory and method of controlling memory  
A cacheable memory access space receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector determines...
7636812 Cache memory control method and cache memory control device  
An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for...
7631146 Processor with cache way prediction and method thereof  
A processor with cache way prediction and method thereof. The processor includes a cache way prediction unit for predicting at least one cache way for selection from a plurality of cache ways. The...
7624234 Directory caches, and methods for operation thereof  
A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into...
7617364 System, method and storage medium for prefetching via memory block tags  
A method and system for memory management are provided. The system includes a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of...
7617366 Method and apparatus for filtering snoop requests using mulitiple snoop caches  
A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have...
7613884 Multiprocessor system and method ensuring coherency between a main memory and a cache memory  
A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a...
7606974 Automatic caching generation in network applications  
Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads...
7600080 Avoiding deadlocks in a multiprocessor system  
In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a...
7596663 Identifying a cache way of a cache access request using information from the microtag and from the micro TLB  
A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data...
7590792 Cache memory analyzing method  
It is done to read information containing an address of a memory at which a cache miss is generated, from a cache memory. The numbers of cache misses generated at each cache miss generated address...
7587556 Store buffer capable of maintaining associated cache information  
A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer...
7580675 Data communication apparatus functioning as ID tag and ID-tag reader and writer  
A data communication apparatus includes an antenna, an analog front-end circuit, and a controller. The analog front-end circuit is connected between the antenna and the controller and includes...
7573880 Set-associative memory architecture for routing tables  
A set-associative architecture (IPStash) restricts routing table prefixes to a limited number of lengths using a controlled, prefix-expansion technique. Since this inflates the routing tables,...
7574572 Cache memory, system, and method of storing data  
A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data...
7574564 Replacement pointer control for set associative cache and method  
A set associative cache includes a plurality of sets, where each set has a plurality of ways. The set associative cache has a plurality of replacement pointers where each set of the plurality of...