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8185459 System, method and computing device for detecting duplicate financial documents  
A method and system are disclosed for identifying in real time duplicate financial documents processed by a financial institution or check clearinghouse. A collection of hash values representative...
8180994 Optimized page programming order for non-volatile memory  
During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit,...
8180965 System and method for cache access prediction  
A cache system includes a cache having a plurality of cache units, a prediction table and a hashing module. The prediction table is utilized to store way information of at least one cache unit...
8176255 Allocating space in dedicated cache ways  
A system comprises a processor core and a cache coupled to the core and comprising at least one cache way dedicated to the core, where the cache way comprises multiple cache lines. The system also...
8151055 Cache accessing using a micro TAG  
A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache...
8145870 System, method and computer program product for application-level cache-mapping awareness and reallocation  
The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service creates a storage map, and sending...
8145848 Processor and method for writeback buffer reuse  
A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a...
8144493 CAM cell memory device  
A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage,...
8131936 Method and apparatus for implementing a combined data/coherency cache  
A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The...
8122192 Data processing apparatus and data processing method  
The data processing apparatus according to an embodiment of the present invention includes: a first processor; a second processor; and an external RAM to/from which the first processor...
8117420 Buffer management structure with selective flush  
A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a...
8117397 Victim cache line selection  
A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include...
8117395 Multi-stage pipeline for cache access  
Some of the embodiments of the present disclosure provide a command processing pipeline to be operatively coupled to a shared cache, the command processing pipeline comprising a command processing...
8108611 Cache memory system  
A cache memory system controlled by an arbiter includes a memory unit having a cache memory whose capacity is changeable, and an invalidation processing unit that requests invalidation of data...
8103894 Power conservation in vertically-striped NUCA caches  
Embodiments that dynamically conserve power in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with...
8095736 Methods and systems for dynamic cache partitioning for distributed applications operating on multiprocessor architectures  
Software, systems and methods are described which provide cache management capabilities. The number of cache sets to be used in each partition of the cache memory space is based on a number of...
8095734 Managing cache line allocations for multiple issue processors  
An apparatus having a cache configured as N-way associative and a controller circuit is disclosed. The controller circuit may be configured to (i) detect one of a cache hit and a cache miss in...
8095731 Mutable object caching  
In one embodiment, a method for caching mutable objects comprises adding to a cache a first cache entry that includes a first object and a first key. Assigning a unique identification to the first...
8078804 Method and arrangement for cache memory management, related processor architecture  
A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for...
8065486 Cache memory control circuit and processor  
A cache memory control circuit includes a selecting section configured to be capable of selecting, in a predetermined order, each way or a predetermined two or more ways of a cache memory having...
8065485 Method and apparatus for determining cache storage locations based on latency requirements  
A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a...
8041895 Translation table coherency mecahanism using cache way and set index write buffers  
Systems and/or methods are presented that provide for recording transactions that occur during a write process for the purpose of recovering the transactions in the event of a power loss. In an...
8037251 Memory compression implementation using non-volatile memory in a multi-node server system with directly attached processor memory  
A method, an apparatus and a program product may enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips may include...
8028128 Method for increasing cache directory associativity classes in a system with a register space memory  
In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity...
8019945 System and method for transactional cache  
A computer-implemented method and system to support transactional caching service comprises configuring a transactional cache that are associated with one or more transactions and one or more work...
7996619 K-way direct mapped cache  
A method and apparatus for a k-way direct mapped cache organization is herein described. Control logic coupled to a cache may associate an address to a way within a plurality based on a first...
7996644 Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache  
An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A resource within a microprocessor...
7995595 Method for efficiently detecting node addresses  
According to one embodiment, node addresses are efficiently detected. For example, a node address is extracted from a packet that is being communicated from a first network to a second network...
7996620 High performance pseudo dynamic 36 bit compare  
A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static...
7984229 Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access  
A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without...
7979640 Cache line duplication in response to a way prediction conflict  
Embodiments of the present invention provide a system that handles way mispredictions in a multi-way cache. The system starts by receiving requests to access cache lines in the multi-way cache....
7966455 Memory compression implementation in a multi-node server system with directly attached processor memory  
A method, apparatus and program product enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips provide the additional...
7966450 Non-volatile hard disk drive cache system and method  
A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The...
7962695 Method and system for integrating SRAM and DRAM architecture in set associative cache  
A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory...
7962694 Partial way hint line replacement algorithm for a snoop filter  
In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based,...
7941606 Identifying a flow identification value mask based on a flow identification value of a packet  
Flow identification value masks are identified based on, and used to mask a flow identification value associated with packets in a router, packet switching or computer system, any other device....
7941605 Methods and apparatus for generating a result based on a lookup result from a lookup operation using an associative memory and processing based on a discriminator portion of a lookup word  
Methods and apparatus are disclosed for generating a result based on a lookup result from a lookup operation using an associative memory and processing based on a discriminator portion of a lookup...
7934054 Re-fetching cache memory enabling alternative operational modes  
A re-fetching cache memory improves efficiency of a system, for example by advantageously sharing the cache memory and/or by increasing performance. When some or all of the cache memory is...
7934114 Method of controlling information processing device, information processing device, program, and program converting method  
The method of controlling an information processing device according to the present invention is a method of controlling an information processing device which includes a processor having a cache...
7930514 Method, system, and computer program product for implementing a dual-addressable cache  
A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a...
7925857 Method for increasing cache directory associativity classes via efficient tag bit reclaimation  
In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address...
7908438 Associative matrix observing methods, systems and computer program products using bit plane representations of selected segments  
Associative matrix compression methods, systems, computer program products and data structures compress an association matrix that contains counts that indicate associations among pairs of...
7904658 Structure for power-efficient cache memory  
A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that...
RE42213 Dynamic reconfigurable memory hierarchy  
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management...
7904675 Cache memory, system, and method of storing data  
A cache memory has a set associative scheme and includes a plurality of ways made up of entries, each entry holding data and a tag; a first holding unit holds, for each way, a priority attribute...
7899993 Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme  
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way...
7900020 Correction of incorrect cache accesses  
The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache...
7882302 Method and system for implementing prioritized refresh of DRAM based cache  
A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most...
7873788 Re-fetching cache memory having coherent re-fetching  
A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or by advantageously sharing the cache memory. When the cache memory is disabled or...
7861041 Second chance replacement mechanism for a highly associative cache memory of a processor  
A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The...