Match Document Document Title
8577989 Method and apparatus for a report cache in a near real-time business intelligence system  
A method of optimizing the delivery of a set of data elements from a first device to a second device. The method includes retrieving from a data source the set of data elements, including a first...
8578097 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8572324 Network on chip with caching restrictions for pages of computer memory  
A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through...
8543775 Preventing unintended loss of transactional data in hardware transactional memory systems  
A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional...
8533399 Cache directory look-up re-use as conflict check mechanism for speculative memory requests  
In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of...
8533396 Memory elements for performing an allocation operation and related methods  
Apparatus for memory elements and related methods for performing an allocate operation are provided. An exemplary memory element includes a plurality of way memory elements and a replacement...
8527708 Detecting address conflicts in a cache memory system  
A cache memory providing improved address conflict detection by reference to a set associative array includes a data array that stores memory blocks, a directory of contents of the data array, and...
8516149 System for operating NFSv2 and NFSv3 clients with federated namespace  
An information retrieval system having: a client adapted for accessing a plurality of file sets stored on one of a plurality of file servers; a plurality of file servers configured to operate with...
8499124 Handling castout cache lines in a victim cache  
A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller,...
8499123 Multi-stage pipeline for cache access  
Embodiments of the present disclosure provide a command processing pipeline operatively coupled to an N-way cache and configured to process a sequence of cache commands. A way of the N ways of the...
8490151 Method and apparatus for performing a multi-role communication using a memory tag  
An approach is presented for performing a multi-role communication using a Radio Frequency (RF) memory tag. The control manager receives a content request, at a memory tag, from a first device...
8489817 Apparatus, system, and method for caching data  
An apparatus, system, and method are disclosed for caching data. A storage request module detects an input/output (“I/O”) request for a storage device cached by solid-state storage media of a...
8464005 Accessing common registers in a multi-core processor  
Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a...
8458404 Programmable cache access protocol to optimize power consumption and performance  
A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring...
8443162 Methods and apparatus for dynamically managing banked memory  
Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The...
8433851 Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing  
A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring...
8423719 Apparatus, processor and method of controlling cache memory  
An apparatus includes a processor which issues a plurality of commands including an identifier for classifying each of the commands, a cache memory which includes a plurality of ways to store a...
8417915 Alias management within a virtually indexed and physically tagged cache memory  
A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12...
8412885 Searching a shared cache by using search hints and masked ways  
In an embodiment of the present invention a method includes: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a...
8397025 Apparatus and method for determining a cache line in an N-way set associative cache using hash functions  
A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is...
8392658 Cache implementing multiple replacement policies  
In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in...
8392651 Data cache way prediction  
A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic...
8364897 Cache organization with an adjustable number of ways  
A method and apparatus for an adjustable number of ways within a cache is herein described. A cache may comprise a plurality of lines addressably organized as a plurality of ways, wherein the...
8364896 Method and apparatus for configuring a unified cache based on an associated error rate  
A method of configuring a unified cache includes identifying unified cache way assignment combinations for an application unit. Each combination has an associated error rate. A combination is...
8352683 Method and system to reduce the power consumption of a memory device  
A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is...
8352688 Preventing unintended loss of transactional data in hardware transactional memory systems  
A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional...
8341355 Reducing energy consumption of set associative caches by reducing checked ways of the set association  
Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are...
8327082 Snoop request arbitration in a data processing system  
A snoop look-up operation is performed in a system having a cache and a first processor. The processor generates requests to the cache for data. A snoop queue is loaded with snoop requests....
8327121 Data cache receive flop bypass  
A microprocessor includes an N-way cache and a logic block that selectively enables and disables the N-way cache for at least one clock cycle if a first register load instructions and a second...
8321632 System and method for supporting mutable object handling  
A computer-implemented method and system can support mutable object handling. The system comprises a cache space that is capable of storing one or more mutable cache objects, and one or more...
8316186 Method and apparatus for managing cache reliability based on an associated error rate  
A method of configuring a cache includes identifying a plurality of cache configurations of a configurable cache for a processor-executable application unit. Each configuration has an associated...
8312216 Data processing apparatus and data processing method  
The data processing apparatus according to an embodiment of the present invention includes: a first processor; a second processor; and an external RAM to/from which the first processor...
8312232 Cache memory control circuit and processor for selecting ways in which a cache memory in which the ways have been divided by a predeterminded division number  
A cache memory control circuit includes a selecting section configured to select each way or two or more ways in a cache memory in which plural ways have been divided by a predetermined division...
8301872 Pipeline configuration protocol and configuration unit communication  
An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular...
8275942 Performance prioritization in multi-threaded processors  
According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority...
8271733 Line allocation in multi-level hierarchical data stores  
A storage apparatus for storing data is disclosed. The storage apparatus comprises: a plurality of stores having storage locations for storing data items, including a level one store and a level...
8271732 System and method to reduce power consumption by partially disabling cache memory  
In one embodiment, a cache memory includes a data array having N ways and M sets and at least one fill buffer coupled to the data array, where the data array is segmented into multiple array...
8250304 Cache memory device and system with set and group limited priority and casting management of I/O type data injection  
A memory device comprising a cache memory with a predetermined amount of cache sets, each cache set comprising a predetermined amount of cache lines. Each cache line is operable to indicate a...
8250300 Cache memory system and method with improved mapping flexibility  
A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives...
8244982 Allocating processor cores with cache memory associativity  
Techniques are generally described related to a multi-core processor with a plurality of processor cores and a cache memory shared by at least some of the processor cores. The multi-core processor...
8244981 Combined transparent/non-transparent cache  
In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a...
8244980 Shared cache performance  
A method and apparatus for improving shared cache performance. In one embodiment, the present invention includes a cache having multiple ways. A locality tester measures a first locality of a...
8234453 Processor having a cache memory which is comprised of a plurality of large scale integration  
To provide an easy way to constitute a processor from a plurality of LSIs, the processor includes: a first LSI containing a processor; a second LSI having a cache memory; and information...
8225046 Method and apparatus for saving power by efficiently disabling ways for a set-associative cache  
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to track consecutive misses to ways of a cache,...
8219780 Mitigating context switch cache miss penalty  
Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a...
8219758 Block-based non-transparent cache  
In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of...
8219996 Computer processor with fairness monitor  
A computer processor includes a fairness monitor for monitoring allocations of a processor resource to requestors. If unfairness is determined, a resource allocator is biased to offset said...
8214602 Efficient load queue snooping  
In one embodiment, a processor comprises a data cache and a load/store unit (LSU). The LSU comprises a queue and a control unit, and each entry in the queue is assigned to a different load that...
8195884 Network on chip with caching restrictions for pages of computer memory  
A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through...
8185694 Testing real page number bits in a cache directory  
Testing real page number bits in a cache directory is provided. A specification of a cache to be tested is retrieved in order to test the real page number bits of the cache directory associated...