AcclaimIP-ad

Match Document Document Title
5210843 Pseudo set-associative memory caching arrangement  
The invention provides a pseudo set-associative memory cacheing arrangement for use in a data processing system comprising a processor interfacing to a main memory and adapted to support a cache...
5210842 Data processor having instruction varied set associative cache boundary accessing  
A data processor having an instruction varied set associative cache boundary access capability provides reduced power consumption and maintains data processor performance. Queued data processor...
5197139 Cache management for multi-processor systems utilizing bulk cross-invalidate  
A store through cache environment managed exclusively grants exclusivity on a large granularity basis. A cross-invalidate is realized for all changed lines via a single transmission when...
5136691 Methods and apparatus for caching interlock variables in an integrated cache memory  
Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of...
5133061 Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses  
An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and a small high speed set-associative...
5091851 Fast multiple-word accesses from a multi-way set-associative cache memory  
A multi-way set-associative cache memory stores data in a plurality of random access memories. Data in the multi-way set-associative cache memory is organized in lines of data. The multi-way...
5073851 Apparatus and method for improved caching in a computer system  
A cache management system for a computer system having a central processing unit, a main memory, and cache memory including a memory management unit for transferring page size blocks of...
5060136 Four-way associative cache with DLAT and separately addressable arrays used for updating certain bits without reading them out first  
A cache storage system is disclosed which has a high speed buffer (cache), a directory-look-aside-table, and apparatus for maintaining binary coded information signifying the order of use of...
5019971 High availability cache organization  
A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory...
5014195 Configurable set associative cache with decoded data element enable lines  
A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag...
4989140 Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit  
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the...
4977498 Data processing system having a data memory interlock coherency scheme  
This invention is directed to a memory system that determines which blocks of a set of associative blocks in cache memory are unavailable for replacement. This is accomplished by operating the...
4942521 Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable  
When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the...
4914582 Cache tag lookaside  
A method of retrieving data from a multi-set cache memory in a computer system. An address, which includes an index, is presented by the processor to the cache memory. The index is utilized to...
4905188 Functional cache memory chip architecture for improved cache access  
An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally...
4899275 Cache-MMU system  
A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set...
4894770 Set associative memory  
In a random access memory, a dynamic memory array is associated with static data buffers. Each static data buffer is connected to the memory array to receive and store a row of data from any...
4736293 Interleaved set-associative memory  
In a processing system (10) comprising a main memory (102) for storing blocks (150) of four contiguous words (160) of information, a cache memory (101) for storing selected ones of the blocks, and...
4736287 Set association memory system  
A memory system for use in a computer which in the preferred embodiment provides two megabytes of capacity per board (up to four boards) is disclosed. An ALU generates an address signal which...
4639891 Signals path control circuitry for a data terminal  
The present invention is related to clearing a communication path and in the alternative blocking said communication path between a data terminal and a main data processor, when it appears, from...
4631660 Addressing system for an associative cache memory  
A memory system which comprises a mainstore for storing lines of data and a buffer store for storing lines of data that are a subset of the data stored in the main store. The buffer store is...
4513367 Cache locking controls in a multiprocessor  
A lock array is provided with bit positions corresponding to each line entry in an associated cache directory. When a lock bit is on, it inhibits the castout, replacement, or invalidation of the...
4493026 Set associative sector cache  
A cache memory for a data processing system having a tag array in which each tag word represents a predetermined plurality or block group of consecutively addressable data block locations in a...
4381541 Buffer memory referencing system for two data words  
A memory accessing system for reading or writing consecutive addressable words is described for use in a set associative memory system. Two high speed buffer memories store words read in blocks...
4370710 Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses  
A cache memory organization is shown using a miss information collection and manipulation system to insure the transparency of cache misses. This system makes use of the fact that the cache memory...
4280177 Implicit address structure and method for accessing an associative memory device  
An implicit address structure and technique are disclosed for rapidly accessing storage registers by eliminating the need for generating a separate address before referencing the register. A...
4156906 Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands  
A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a store having a plurality of word locations arranged into...
4151593 Memory module with means for controlling internal timing  
A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory...
4122530 Data management method and system for random access electron beam memory  
A data recording and readback subsystem for digital computer systems employing random access electron beam memories having an electron beam write/read apparatus for recording data to be stored on...
3938097 Memory and buffer arrangement for digital computers  
Random access storage facilities for the CPU of a computer are cascaded in that a facility of relatively fast access speed holds a subset of information held in a facility of lower speed. Memory...
3845474 CACHE STORE CLEARING OPERATION FOR MULTIPROCESSOR MODE  
In a multiprocessor data processing system, all processors must have access to certain communications tables stored in the main memory shared by the processors. Each processor has a cache store...
3840862 STATUS INDICATOR APPARATUS FOR TAG DIRECTORY IN ASSOCIATIVE STORES  
A four level directory is used to retain "tags" identifying the address of data information stored in a cache store. A three bit storage unit stores a full/empty status indication of each level of...
3813648 APPARATUS AND PROCESS FOR DISTRIBUTION OF OPERATION DEMANDS IN A PROGRAMMED CONTROLLED DATA EXCHANGE SYSTEM  
A process and apparatus are described for operating a program controlled data exchange system having at least one central memory constructed in the form of a multistorage unit containing programs...
3611315 MEMORY CONTROL SYSTEM FOR CONTROLLING A BUFFER MEMORY  
A memory control system for a computer having a main memory, a central processor, a buffer memory and a memory controller. The buffer memory comprises a plurality of sectors each consisting of a...
3541529 REPLACEMENT SYSTEM  
3350698 Associative data processing system  
3339183 Copy memory for a digital processor  
3292153 Memory system