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5729712 Smart fill system for multiple cache network  
An optimization system for the cache-fill operation in a multi-set cache memory operates to select that cache-set which indicates it has invalid data therein and/or also indicates that an...
5724547 LRU pointer updating in a controller for two-way set associative cache  
A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses....
5721863 Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address  
A structure and method of operation of a cache memory are provided. The cache memory is organized such that the data on a given line of any page of the main memory is stored on the same line of a...
5717892 Selectively operable cache memory  
A cache memory in which the address of a required data item is compared with address data stored in a plurality of tag memory sections, a match indicating that the required data item is stored in...
5715426 Set-associative cache memory with shared sense amplifiers  
A cache memory employs a set-associative method for associating cached data with main storage data. The cache memory comprises memory cells MSs, sense amplifiers SAW0 through SAWs-1, s way hit...
5710905 Cache controller for a non-symetric cache system  
A cache controller includes a hit determination circuit that is adapted to handle a non-symmetric cache. This hit determination circuit includes symmetric match circuit having a first input port...
5701431 Method and system for randomly selecting a cache set for cache fill operations  
A central processor is serviced by a multi-way cache module having N cache sets some of which can be taken off-line by a maintenance subsystem. Masking logic is provided to control the...
5696935 Multiported cache and systems  
A cache memory is provided with a plurality of address ports and a corresponding plurality of tag ports for use with multiple pipes in a pipelined system. One of the address ports is dedicated to...
5684976 Method and system for reduced address tags storage within a directory having a tree-like data structure  
An efficient method and system within a data processing system for storing address tags are disclosed, which include a tag directory having a plurality of congruence classes, wherein each...
5675765 Cache memory system with independently accessible subdivided cache tag arrays  
Two independently accessible subdivided cache tag arrays and a cache control logic is provided to a set associative cache system. Each tag entry is stored in two subdivided cache tag arrays, a...
5668968 Two-level virtual/real set associative cache system and method with improved synonym detection  
A two-level virtual/real cache system, and a method for detecting and resolving synonyms in the two-level virtual/real cache system, are described. Lines of a first level virtual cache are tagged...
5659699 Method and system for managing cache memory utilizing multiple hash functions  
In a data processing system, a tag memory is divided into a first tag memory portion and a second tag memory portion. Next, an address for recalling requested data is generated by a central...
5651135 Multi-way set associative cache system in which the number of lines per set differs and loading depends on access frequency  
A set associative cache system in a computer system having a lower memory is provided with a plurality of cache memory sets. A cache data memory contains a plurality of cache lines to store data...
5649154 Cache memory system having secondary cache integrated with primary cache for use with VLSI circuits  
A cache memory system with a secondary cache integrated with a direct mapped primary cache in a single structure preferably constructed on a VLSI chip. The secondary cache uses the same output...
5649155 Cache memory accessed by continuation requests  
In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a...
5623627 Computer memory architecture including a replacement cache  
A microprocessor is provided with an integral, two level cache memory architecture. The microprocessor includes a microprocessor core and a set associative first level cache both located on a...
5619676 High speed semiconductor memory including a cache-prefetch prediction controller including a register for storing previous cycle requested addresses  
The high speed semiconductor memory includes at least one memory module and a cache controller. The at least one memory module includes a plurality of memory cells for storing data and a cache...
5611072 Cache with an extended single cycle read/write system and method  
A method for updating a LRU array in a cache having a RAM. The LRU array has a self-timing signal for the read operation of the LRU array, in conjunction with a cache RAM read cycle. According to...
5586279 Data processing system and method for testing a data processor having a cache memory  
A cached processor (2) comprises a cache memory (8') having mode switching means for selecting an address capture mode whereby information, such as data and/or instructions, can be captured and...
5584014 Apparatus and method to preserve data in a set associative memory device  
An apparatus and method to dynamically partition a set-associative memory device is described. The apparatus includes a set identification device to specify a group of set-associative data blocks...
5581734 Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity  
A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each...
5568632 Method and apparatus for cache memory  
The present invention is an improved method and apparatus for selecting and replacing a block of a set of cache memory. The present invention provides for the weighted random replacement of blocks...
5564034 Cache memory with a write buffer indicating way selection  
The present invention discloses a 2-way set-associative cache memory incorporating thereinto a write buffer. Tag entries corresponding to data entries within each bank are added valid bits and...
5553262 Memory apparatus and method capable of setting attribute of information to be cached  
A cache memory apparatus allocates memory regions on the basis of information attributes. The required memory region corresponding to the attribute is accessed before caching is implemented. This...
5550995 Memory cache with automatic alliased entry invalidation and method of operation  
A memory cache (14) has a semi-associative cache array (50), a cache reload buffer (40), and a cache reload buffer driver (42). The memory cache writes received data to the cache reload buffer and...
5551001 Master-slave cache system for instruction and data cache memories  
A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline...
5548742 Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory  
A two-way set-associative cache memory includes both a set array and a data array in one embodiment. The data array comprises multiple elements, each of which can contain a cache line. The set...
5539894 Method and apparatus for optimizing a sector cache tag, block and sub-block structure base on main memory size  
A sector cache tag structure for a computer system with a cache memory and a maximum amount of system memory is disclosed. Upon initial power-up of the computer system, the amount of system memory...
5537570 Cache with a tag duplicate fault avoidance system and method  
A method for avoiding a tag duplicate fault. The method includes the steps of using a master - slave tag; selecting a first tag as a master and a second tag as a slave; inhibiting the second tag...
5530833 Apparatus and method for updating LRU pointer in a controller for two-way set associative cache  
A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses....
5522056 Cache memory with plurality of congruence sets and sense amplifiers shared among the congruence sets  
A cache memory with a data memory divided into a plurality of word arrays, each of which is selectable by a word select indicator. Each word array is further divided into a plurality of bit...
5493667 Apparatus and method for an instruction cache locking scheme  
An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two...
5479641 Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking  
A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag...
5450565 Circuit and method for selecting a set in a set associative cache  
A set select circuit and method for selecting a set in a set associative cache in a microprocessor. The set select circuit, responsive to a main clock, includes an input latch coupled to receive...
5418922 History table for set prediction for accessing a set associative cache  
A cache control maintains a history table SETLAT for the prediction of line entry (i.e., set member) within a congruence class for cache accessing. For a given cache access, a SETLAT entry can be...
5404486 Processor having a stall cache and associated method for preventing instruction stream stalls during load and store instructions in a pipelined computer system  
A central processing unit of a computer system which has an arithmetic logic unit, a register file, an instruction decode/fetch instruction data unit, a bus interface, a multiplexer and a stall...
5392417 Processor cycle tracking in a controller for two-way set associative cache  
A processor communicates over a memory bus with a main memory and a cache by asserting an address strobe signal (ADS) to initiate a memory access. The cache includes a cache controller and a tag...
5392414 Rapid data retrieval from data storage structures using prior access predictive annotations  
A data storage structure and its complementary selection data storage structure is provided with a complementary predictive annotation storage structure comprising a number of corresponding...
5367659 Tag initialization in a controller for two-way set associative cache  
A cache controller tag ram is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The two ways, a...
5367653 Reconfigurable multi-way associative cache memory  
A reconfigurable set associative cache memory can be reconfigured from 2x way to 2y way set associative cache memory by effectively merging a predetermined number of least significant bits of the...
5353424 Fast tag compare and bank select in set associative cache  
A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data...
5325504 Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system  
A method and apparatus for incorporating cache line replacement and cache write policy information into the tag directories in a cache system. In a 2 way set-associative cache, one bit in each...
5325511 True least recently used replacement method and apparatus  
An apparatus for performing Least Recently Used techniques for a four way set associative cache system which includes a random access memory (RAM) which stores the ways representing the least...
5317718 Data processing system and method with prefetch buffers  
A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). Misses in the cache (18 or 20) that...
5313613 Execution of storage-immediate and storage-storage instructions within cache buffer storage  
A cache storage system having hardware for in-cache execution of storage-storage and storage-immediate instructions thereby obviating the need for data to be moved from the cache to a separate...
5301296 Microprocessor with cache memory  
A microprocessor which has a plurality of cache memory units with plural ways, a plurality of data buses each having different bus width, and a write way control unit or an address control unit...
5261066 Data processing system and method with small fully-associative cache and prefetch buffers  
A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). misses in the cache (18 or 20) that...
5235697 Set prediction cache memory system using bits of the main memory address  
The set-prediction cache memory system comprises an extension of a set-associative cache memory system which operates in parallel to the set-associative structure to increase the overall speed of...
5218687 Method and apparatus for fast memory access in a computer system  
A method and apparatus for fast memory access in a computer system employing a high-speed associative memory for storing extracts that each include an address and an associated information...
5210845 Controller for two-way set associative cache  
A cache controller (10) which sits in parallel with a microprocessor bus (14, 15, 29) so as not to impede system response in the event of a cache miss. The cache controller tagram (24) is...