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5966734 Resizable and relocatable memory scratch pad as a cache slice  
A cache system supports a re-sizable software-managed fast scratch pad that is implemented as a cache-slice. A processor register indicates the size and base address of the scratch pad....
5937432 Associative storage and associative storing method  
An associative storage includes: a plurality of storage elements having at least one internal signal outputting element for outputting an internal outputting signal toward another storage element...
5920888 Cache memory system having high and low speed and power consumption modes in which different ways are selectively enabled depending on a reference clock frequency  
A cache memory automatically sets a low-, semi-, or high-speed mode operation according to a result of comparison between a half-period of a reference clock signal and a pulse width of a reference...
5918245 Microprocessor having a cache memory system using multi-level cache set prediction  
A cache structure for a microprocessor which provides set-prediction information for a separate, second-level cache, and a method for improving cache accessing, are provided. In the event of a...
5913223 Low power set associative cache memory  
A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion...
5909695 Maximal concurrent lookup cache for computing systems having a multi-threaded environment  
A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry being identified by an entry number....
5909694 Multiway associative external microprocessor cache  
A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for...
5905997 Set-associative cache memory utilizing a single bank of physical memory  
Multiple banks associated with a multiple set associative cache are stored in a single chip, reducing the number of SRAMs required. Certain status information for the second level (L2) cache is...
5897655 System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference  
In a method and system for storing information within a set of a cache memory, the set has multiple locations. The information is stored at a selected one of the locations. The selected location...
5897651 Information handling system including a direct access set associative cache and method for accessing same  
An information handling system includes a cache memory architecture which includes a means for performing a direct lookup by identifying the double word in the cache using the congruence class ID...
5895501 Virtual memory system for vector based computer systems  
A virtual memory management system for a vector based processing system detects early page or segment faults allowing pipelined instructions to be halted and resumed once the pages or segments...
5893146 Cache structure having a reduced tag comparison to enable data transfer from said cache  
A cache including a tag storage which compares a portion of the tag address (a "mini-tag") to a respective portion of a request address is provided. If the mini-tag matches, then the way...
5893143 Parallel processing unit with cache memories storing NO-OP mask bits for instructions  
Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache...
5875465 Cache control circuit having a pseudo random address generator  
A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache...
5870616 System and method for reducing power consumption in an electronic circuit  
While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache...
5860085 Instruction set for a content addressable memory array with read/write circuits and an interface register logic block  
An associative processing memory system for concurrent data searching and concurrent data processing which includes content addressable memory (CAM) array having multiple CAM words; a multiplexer...
5860093 Reduced instruction processor/storage controller interface  
Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins...
5860097 Associative cache memory with improved hit time  
An associative cache memory for a computer with improved cache hit times. All possible data items are presented to bus driver circuits, thereby deferring data selection as long as possible....
5854943 Speed efficient cache output selector circuitry based on tag compare and data organization  
A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data...
5848428 Sense amplifier decoding in a memory device to reduce power consumption  
A multiple-way cache memory system incorporating circuitry for selectively enabling the sense amplifiers in a given memory bank only when the memory bank contains data that is being accessed. In...
5845320 Circuit and method to implement a least recently used cache set replacement technique  
A circuit for controlling which set of a four-way set associated cache memory receives data for storage includes a memory array for storing six bits of information representative of the relative...
5845324 Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access  
A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system...
5845323 Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time  
A way prediction structure is provided which predicts a way of an associative cache in which an access will hit, and causes the data bytes from the predicted way to be conveyed as the output of...
5835948 Single bank, multiple way cache memory  
In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of...
5835928 Circuitry and method for relating first and second memory locations where the second memory location stores information from the first memory location  
A first group of memory locations stores information. The first group is arranged into multiple congruence classes of memory locations. The congruence classes include a first congruence class...
5835945 Memory system with write buffer, prefetch and internal caches  
A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with...
5835951 Branch processing unit with target cache read prioritization protocol for handling multiple hits  
An up/dn read prioritization protocol is used to select between multiple hits in a set associative cache. Each set has associated with it an up/dn priority bit that controls read prioritization...
5831889 Cache memory device and manufacturing method thereof  
A method is for manufacturing a cache memory device for writing cache data into and reading cache data from a storing region of a memory cell array designated according to a portion of an address...
5822756 Microprocessor cache memory way prediction based on the way of a previous memory read  
In a microcomputer system using a multiple-way cache memory subsystem, the way of the next microprocessor operation is predicted, and either the output enables of the cache are predriven, or, in a...
5809522 Microprocessor system with process identification tag entries to reduce cache flushing after a context switch  
An x86 microprocessor system with a process identification system which stores a number assigned to each process run by the microprocessor system and associates this number with instructions,...
5809535 Cache memory control apparatus utilizing a bit as a second valid bit in a tag in a first mode and as an additional address bit in a second mode  
A cache memory control apparatus for a cache memory having a data memory, includes an address array, a valid bit register, a comparator, and a dual-purpose register. The dual-purpose register...
5809528 Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory  
An architecture and method of implementing an invalid data handling least recently used replacement mechanism in a cache memory system is provided that includes a first register stack, a second...
5805855 Data cache array having multiple content addressable fields per cache line  
An interleaved data cache array which is divided into two subarrays. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a...
5802594 Single phase pseudo-static instruction translation look-aside buffer  
An instruction translation look-aside buffer (iTLB) for attaining very high data processing throughput comprises a 2n -way set associative data array having m sets, where m and n are both integers...
5802602 Method and apparatus for performing reads of related data from a set-associative cache memory  
Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding...
5802572 Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache  
A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data...
5802586 Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor  
A multiple-way, set associative cache memory (20) allows burst read and burst write operations to occur simultaneously on different columns within a memory block during a read-modify-write...
5781923 Adding a field to the cache tag in a computer system to indicate byte ordering  
A system for indicating byte-order format information of multi-byte data contained in a cache memory. A plurality of cache lines resident in the cache memory each include cache line data copied...
5778427 Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure  
The present invention provides a cache manager (CM) for use with an address translation table (ATT) which take advantage of way information, available when a cache line is first cached, for...
5778424 Distributed placement, variable-size cache architecture  
A distributed variable-size cache placement architecture includes plural cache storage units (CSUs), each of which includes a CSU control logic, an address director, a data director, a placement...
5778428 Programmable high performance mode for multi-way associative cache/memory designs  
The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the...
5765035 Recorder buffer capable of detecting dependencies between accesses to a pair of caches  
A dependency checking structure is provided which compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode...
5761715 Information processing device and cache memory with adjustable number of ways to reduce power consumption based on cache miss ratio  
In a cache memory of a set associative type, a cache-miss rate measuring circuit 140 measures the cache-miss rate during way access operation, the way number control circuit 150 determines the...
5752261 Method and apparatus for detecting thrashing in a cache memory  
A cache controller for a cache memory having a number of cache lines includes a page index monitor and a page index tracker coupled to the page index monitor. The page index monitor is configured...
5752069 Superscalar microprocessor employing away prediction structure  
A superscalar microprocessor employing a way prediction structure is provided. The way prediction structure predicts a way of an associative cache in which an access will hit, and causes the data...
5752275 Translation look-aside buffer including a single page size translation unit  
A method and apparatus for use in a computer system to translate virtual addresses into translated addresses. According to one aspect of the invention, a dynamically configurable translation unit...
5749087 Method and apparatus for maintaining n-way associative directories utilizing a content addressable memory  
A method and apparatus are provided for maintaining a N-way associative directory utilizing a content addressable memory (CAM). A congruence class from the N-way associative directory including a...
5742790 Detection circuit for identical and simultaneous access in a parallel processor system with a multi-way multi-port cache  
A detection circuit for detecting a simultaneous and identical access signal in a parallel processor. The detection circuit includes a cache memory, having multiple ports, for generating a SAME...
5737752 Cache replacement mechanism  
An n-way set-associative cache (where n is an integer greater than 1), includes a replacement mechanism for selecting a cache line for replacement. Each cache line has an associated priority tag...
5732242 Consistently specifying way destinations through prefetching hints  
A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for...