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6233655 Method for Quad-word Storing into 2-way interleaved L1 cache  
A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and...
6223255 Microprocessor with an instruction level reconfigurable n-way cache  
A microprocessor includes a multiply-accumulate unit (MAU) for performing high-speed signal processing operations. First and second caches provide first and second operands (x, y) directly to the...
6216198 Cache memory accessible for continuous data without tag array indexing  
A tag array includes, corresponding to each line, backward and forward links for holding line numbers for storing adjacent data included in continuous data. For storing the continuous data in the...
6212616 Even/odd cache directory mechanism  
The index field of an address maps to low order cache directory address lines. The remaining cache directory address line, the highest order line, is indexed by the parity of the address tag for...
6205520 Method and apparatus for implementing non-temporal stores  
A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming...
6195738 Combined associative processor and random access memory architecture  
An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the...
6192458 High performance cache directory addressing scheme for variable cache sizes utilizing associativity  
To avoid multiplexing within the critical address paths, the same address field is employed as a index to the cache directory and cache memory regardless of the cache memory size. An increase in...
6185657 Multi-way cache apparatus and method  
Apparatus having a multi-way cache (18), the apparatus including a first user controllable element (102, 104, or 106) having a predetermined first attribute corresponding to a first way of the...
6175902 Method and apparatus for maintaining a time order by physical ordering in a memory  
A method and arrangement for maintaining a time order of entries in a memory determines a row in which the entry will be stored, the memory being logically divided into rows and columns. The...
6161166 Instruction cache for multithreaded processor  
A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory...
6157980 Cache directory addressing scheme for variable cache sizes  
To avoid multiplexing within the critical address path, the same field from an address is employed to index rows within a cache directory and memory regardless of the size of the cache memory....
6145055 Cache memory having flags for inhibiting rewrite of replacement algorithm area corresponding to fault cell and information processing system having such a cache memory  
When a fault cell is found in an initial state at the time of power-on, LRU bit is rewritten so that the LRU bit does not take an entry corresponding to a fault cell as an object of updating and...
6138211 High-performance LRU memory capable of supporting multiple ports  
In a high performance microprocessor adopting a superscalar technique, necessarily using a cache memory, TLB, BTB and etc. and being implemented by 4-way set associative, there is provided an LRU...
6138209 Data processing system and multi-way set associative cache utilizing class predict data structure and method thereof  
A data processing system and method thereof utilize a unique cache architecture that performs class prediction in a multi-way set associative cache during either or both of handling a memory...
6138225 Address translation system having first and second translation look aside buffers  
A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a...
6138226 Logical cache memory storing logical and physical address information for resolving synonym problems  
Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area...
6131143 Multi-way associative storage type cache memory  
An associative storage type cache memory is disclosed, which comprises a decoder for decoding an entry address designated by a data processing unit, a first tag memory for storing higher-order...
6125426 Associative memory device  
An associative memory device having a high speed and good performance is provided without degrading the simple design of a peripheral circuit of a conventional associative memory. The associative...
6122709 Cache with reduced tag information storage  
A cache memory system including a cache memory having a plurality of cache lines. An index portion of a tag array includes an n-bit pointer entry for every cache line. A shared tag portion of a...
6115792 Way prediction logic for cache array  
A set-associative cache memory configured to use multiple portions of a requested address in parallel to quickly access data from a data array based upon stored way predictions. The cache memory...
6112278 Method to store initiator information for SCSI data transfer  
In a data processing system having few initiators or several initiators with the same parameters, support for all initiators is provided by storing sets of parameters and corresponding lists of...
6108745 Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes  
An address routing scheme supports a variety of memory sizes and interleaving schemes. In one embodiment, any address bit provided by the processor can be routed to any bank, row, or column bit,...
6105111 Method and apparatus for providing a cache management technique  
A cache technique for maximizing cache efficiency by assigning ages to elements which access the cache, is described. In one embodiment, the cache technique includes receiving a first element of a...
6101578 Method and apparatus for providing test mode access to an instruction cache and microcode ROM  
A method and apparatus for providing full accessibility to on-chip instruction cache and microcode ROM are described. A dummy tag and a dummy instruction are written into a cache tag array and an...
6101595 Fetching instructions from an instruction cache using sequential way prediction  
An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in...
6098150 Method and apparatus for fetching information from a cache memory  
The present invention relates to a method and apparatus for efficiently outputting words from an N-way set-associative cache. In one embodiment, the cache tags contain information indicating which...
6094694 System for storing new messages in both full-length and abbreviated versions of message expiration data, and eliminating old, expired messages when a message is retrieved  
A data processing apparatus runs a messaging and queuing software package whereby messages received at the data processing apparatus are stored in a message queue. The apparatus has: a processor;...
6092151 CRT update apparatus and method for variable size cache memory using tags and address boundary determination  
A portion of cache memory may be converted from temporary memory to fixed memory such that the instructions, data or both instructions and data stored at the cache memory address are fixed or...
6078995 Methods and apparatus for true least recently used (LRU) bit encoding for multi-way associative caches  
Two techniques are provided for implementing a least recently used (LRU) replacement algorithm for multi-way associative caches. A first method uses a special encoding of the LRU list to allow...
6078993 Data supplying apparatus for independently performing hit determination and data access  
An address buffer that stores information used to access a data memory is disposed in a cache unit that supplies data such as an instruction code to an instruction executing unit. A tag memory and...
6078992 Dirty line cache  
A technique for providing a dirty line cache to supplement a cache memory, in order to improve caching performance for a processor in a computer system. A fully-associative cache memory is coupled...
6076140 Set associative cache memory system with reduced power consumption  
A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built...
6076141 Look-up switch accelerator and method of operating same  
A look-up switch accelerator which includes an associative memory for storing information associated with one or more look-up switch statements. For each look-up switch statement, this information...
6067600 Combined cache tag and data memory architecture  
A cache memory circuit for use in a cache memory system having a predetermined width is comprised of a memory array divided into a cache data memory portion and a tag memory portion. The...
6065091 Translation look-aside buffer slice circuit and method of operation  
For use in an x-86 processor having a physically-addressable cache and an associated translation look-aside buffer (primary TLB) that stores corresponding logical and physical addresses for...
6058456 Software-managed programmable unified/split caching mechanism for instructions and data  
A method of allocating a cache used by a processor of a computer system between instructions and data is disclosed. Program instructions are loaded in the processor for monitoring relative usage...
6047358 Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups  
A computer system, a cache memory and a process, each enabling a cache replacement policy with locking. The computer system comprises a processing device and a memory system, the memory system...
6026470 Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels  
A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function,...
6021461 Method for reducing power consumption in a set associative cache memory system  
A method for accessing a cache memory which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address...
6016545 Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor  
A microprocessor stores cache-line-related data (e.g. branch predictions or predecode data, in the illustrated embodiments) in a storage which includes fewer storage locations than the number of...
6016534 Data processing system for controlling operation of a sense amplifier in a cache  
A cache memory device having circuitry for controlling operation of a sense amplifier for accessing an array in the data processing system including a cache memory device includes circuitry for...
6006309 Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache  
A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU...
6006310 Single memory device that functions as a multi-way set associative cache memory  
A memory device provides for multi-way set associative burst SRAM (static random access memory) cache memory in a single device or package. In one embodiment input address bit A2 is used to...
6000014 Software-managed programmable congruence class caching mechanism  
A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. Program instructions are loaded in the processor for modifying original...
5983322 Hardware-managed programmable congruence class caching mechanism  
A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of...
5978888 Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels  
A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function,...
5978887 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Cache memory with dual-way arrays and multiplexed parallel output
 
A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense...
5974510 Method for testing the non-cacheable region functioning of a cache memory controller  
A method for testing the functioning of a non-cacheable region within a cache having a cache controller programmed with a write-back write policy and a non-cacheable region included in an image...
5974505 Method and system for reducing power consumption of a non-blocking cache within a data processing system  
A method and system for reducing power consumption of a non-blocking cache memory within a data processing system is disclosed. In accordance with a method and system of the present disclosure, a...
5970509 Hit determination circuit for selecting a data set based on miss determinations in other data sets and method of operation  
For use in an x86-compatible processor having a translation look-aside buffer (TLB) and an associated cache with first and second ways, a hit indication circuit for, and method of, indicating when...