Match Document Document Title
6449693 Method and apparatus for improving caching within a processor system  
A processor system is provided that comprises a plurality of L0 caches, a processor having a plurality of execution units, and an L1 cache for caching any data and instructions used by the...
6449691 Asymmetrical cache properties within a hashed storage subsystem  
A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by...
6446168 Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity  
A method of dynamically switching mapping schemes for cache includes a microprocessor, a first mapping scheme, a second mapping scheme and switching circuitry for switching between the first...
6446171 Method and apparatus for tracking and update of LRU algorithm using vectors  
An apparatus and method for tracking the LRU state of memory locations in data ways or nodes is provided. Vectors are utilized between each entry in each node with the direction of the vectors...
6446166 Method for upper level cache victim selection management by a lower level cache  
A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested...
6438653 Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system  
A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control...
6434671 Software-controlled cache memory compartmentalization  
A method and apparatus for controlling compartmentalization of a cache memory. A cache memory including a plurality of storage components receives one or more externally generated cache...
6434670 Method and apparatus for efficiently managing caches with non-power-of-two congruence classes  
A method and apparatus for efficiently managing caches with non-power-of-two congruence classes allows for increasing the number of congruence classes in a cache when not enough area is available...
6434669 Method of cache management to dynamically update information-type dependent cache policies  
A set associative cache includes a cache controller, a directory, and an array including at least one congruence class containing a plurality of sets. The plurality of sets are partitioned into...
6434668 Method of cache management to store information in particular regions of the cache according to information-type  
A set associative cache includes a number of congruence classes that each contain a plurality of sets, a directory, and a cache controller. The directory indicates, for each congruence class,...
6430656 Cache and management method using combined software and hardware congruence class selectors  
A cache memory provides a mechanism for storing and retrieving values wherein a hardware mechanism such as a partial address field selector is combined with an software generated selector in order...
6427192 Method and apparatus for caching victimized branch predictions  
A microprocessor capable of caching victimized branch prediction information is disclosed. Branch prediction information is generated as branch instructions are executed over time. This prediction...
6425056 Method for controlling a direct mapped or two way set associative cache memory in a computer system  
A method is described for controlling a cache memory that may be either a direct-mapped or two-way set-associative cache. The described method is performed by a configurable cache controller. The...
6425058 Cache management mechanism to enable information-type dependent cache policies  
A set associative cache includes a cache controller, a directory, and an array including at least one congruence class containing a plurality of sets. The plurality of sets are partitioned into...
6425055 Way-predicting cache memory  
An apparatus and method for accessing a cache memory. In a cache memory, an address is received that includes a set field and a partial tag field, the set field and the partial tag field together...
6421761 Partitioned cache and management method for selectively caching data by type  
A partitioned cache and management method for selectively caching data by type improves the efficiency of a cache memory by partitioning congruence class sets for storage of particular data types...
6418525 Method and apparatus for reducing latency in set-associative caches using set prediction  
A method and apparatus for storing and utilizing set prediction information regarding which set of a set-associative memory will be accessed for enhancing performance of the set-associative memory...
6415293 Memory device including an associative memory for the storage of data belonging to a plurality of classes  
A memory device having an associative memory for the storage of data belonging to a plurality of classes. The associative memory has a plurality of memory locations aligned along rows and columns...
6412051 System and method for controlling a memory array in an information handling system  
A system and method for allowing operation of a storage array after a failure within a set of an n-way set associative cache includes determining that there is a failure in a bit line in the...
6412038 Integral modular cache for a processor  
An integral modular cache. One embodiment includes a processor portion and a cache memory portion. The cache memory portion includes an array portion having tag logic and a set portion. The array...
6408364 Apparatus and method for implementing a least recently used cache replacement algorithm  
A least recently used (LRU) cache replacement algorithm is implemented with a set of N pointer registers that point to respective ways of an N-way set of memory blocks. One of the pointer...
6405287 Cache line replacement using cache status to bias way selection  
A method for determining which way of an N-way set associative cache should be filled with replacement data upon generation of a cache miss when all of the ways contain valid data. A first choice...
6397298 Cache memory having a programmable cache replacement scheme  
A cache memory having a programmable cache replacement scheme is disclosed. After a cache “miss,” a linefill operation is first preformed on a cache line. Subsequent to the linefill operation, the...
6389524 Decoding device with associative memory permitting variable-length keyword comparisons  
A tag array retains a plurality of tag data, and performs matching of the tag data with a retrieval keyword. The tag array includes matching circuits provided corresponding to the tag data. Each...
6385696 Embedded cache with way size bigger than page size  
A processor having an embedded cache memory, the cache including a tag array that is split into first and second halves each having N ways, the first half storing an upper M sets and the second...
6385697 System and method for cache process  
In a cache system, a non-FSA (Full-Set Associative) cash table such as a DM (Direct Mapping) cache table is coupled with an FSA cache table. Tag comparison for cache hit judgment is executed...
6378042 Caching associative memory  
A system and method for operating an associative memory cache device in a computer system. The system comprises a search client configured to search for data in a caching associative memory such...
6370622 Method and apparatus for curious and column caching  
Curious caching improves upon cache snooping by allowing a snooping cache to insert data from snooped bus operations that is not currently in the cache and independent of any prior accesses to the...
6366978 Cache memory  
A cache memory system 22 is described in which a content addressable memory 24 and a cache RAM memory 28 are provided. Each content addressable storage row has an associated hit line 18 and an...
6356980 Method and system for bypassing cache levels when casting out from an upper level cache  
A method and system for bypassing cache levels when storing data castout from an upper level cache provides a memory hierarchy that can selectively skip one more more intermediate levels when...
6356990 Set-associative cache memory having a built-in set prediction array  
A set-associative cache memory having a built-in set prediction array is disclosed. The cache memory can be accessed via an effective address having a tag field, a line index field, and a byte...
6351797 Translation look-aside buffer for storing region configuration bits and method of operation  
There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address...
6351789 Built-in self-test circuit and method for validating an associative data array  
There is disclosed, for use in a processing device having an N-way set associative data array (such as an L1 cache), a built-in self-test (BIST) circuit for testing the validity of storage...
6349362 Scheme to partition a large lookaside buffer into an L2 cache array  
A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n−1)-way associative cache, so that one associative column of the...
6345336 Instruction cache memory includes a clock gate circuit for selectively supplying a clock signal to tag RAM to reduce power consumption  
An instruction cache memory (12) includes a clock gate circuit (26) for controlling the supply of a clock signal (CLK) to tag RAM (22). The clock gate circuit (22) supplies the clock signal (CLK)...
6343344 System bus directory snooping mechanism for read/castout (RCO) address transaction  
In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the...
6334170 Multi-way cache expansion circuit architecture  
An expandable-set, tag, cache circuit for use with a data cache memory comprises a tag memory divided into a first set and a second set for storing, under a single address location, first and...
6332179 Allocation for back-to-back misses in a directory based cache  
A preferred embodiment of the present invention includes a memory caching system that uses a method for allocating blocks of memory by: determining if the contents at a selected memory address are...
6330556 Data structure partitioning to optimize cache utilization  
Fields which are individually addressable data elements in data structures are reordered to improve the efficiency of cache line access. Temporal data regarding the referencing of such fields is...
6321297 Avoiding tag compares during writes in multi-level cache hierarchy  
A method and apparatus for avoiding tag compares when writing to a cache. In a cache hierarchy, location information of the cache entries are linked and supplied to the other caches, during...
6304962 Method and apparatus for prefetching superblocks in a computer processing system  
A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch...
6292870 Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units  
Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of...
6292871 Loading accessed data from a prefetch buffer to a least recently used position in a cache  
A cache memory system comprises a cache 4, a prefetch store 5, and a memory controller 3. The controller 3 receives requests from a processor 1 for access to lines of data stored in a memory 2 and...
6275901 Computer system having a set associative cache memory with sequentially accessed on-chip address tag array and off-chip data array  
A cache controller is associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where addresses are compared with...
6272597 Dual-ported, pipelined, two level cache system  
A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The on-chip cache memory has two levels. The first level is optimized for low latency...
6272596 Data processor  
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the...
6272595 N-way set-associative cache memory which includes a store hit buffer for improved data access  
A cache memory circuit is disclosed that includes a store hit buffer that buffers write operations to the cache memory circuit and that removes write operations from the critical speed path for...
6256709 Method for storing data in two-way set associative odd and even banks of a cache memory  
Two-way set associative data is stored in a cache memory array. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are...
6240485 Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system  
A method and apparatus for implementing a LEARN instruction in a depth cascaded content address memory (CAM) system. Each CAM device in the CAM system may include a CAM array, an input coupled to...
6236585 Dynamic, data-precharged, variable-entry-length, content addressable memory circuit architecture with multiple transistor threshold voltage extensions  
A dynamic, data-precharged, variable-entry-length content addressable memory circuit architecture. A match at a particular data bit is found employing precharge/conditional discharge domino logic....