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7613894 |
Power loss recovery in non-volatile memory
A method that may be used in a no bit-twiddling file system of a non-volatile memory. The method comprises writing to a non-volatile memory a data sector of a file system, and writing to the...
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7610449 |
Apparatus and method for saving power in a trace cache
A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional...
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7610433 |
Memory controller interface
A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory (SRAM) memory devices to instead operate using NAND...
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7606975 |
Trace cache for efficient self-modifying code processing
A trace cache for efficient self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache even during...
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7587566 |
Realtime memory management via locking realtime threads and related data structures
The present invention is directed to a method and system for minimizing memory access latency during realtime processing. The method includes a mechanism for marking information that will be...
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7587555 |
Program thread synchronization
The present invention is a method of and system for program thread synchronization. In accordance with an embodiment of the invention, a method of synchronizing program threads for one or more...
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7568112 |
Data access control method for tamper resistant microprocessor using cache memory
In a tamper resistant microprocessor having a cache memory, the cache memory stores the decrypted execution code or data into one of cache lines provided in the cache memory, each cache line having...
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7568076 |
Variable store gather window
A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue...
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7568070 |
Instruction cache having fixed number of variable length instructions
A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each...
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7555607 |
Program thread syncronization for instruction cachelines
In a method of and system for program thread synchronization, an instruction cache line is determined each of a plurality of program threads to be synchronized. For each processor executing one or...
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7552283 |
Efficient memory hierarchy management
In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for...
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7543127 |
Computer system
A technology for allowing the smooth acquisition of required data when a processor switches working modes in a computer system is provided. According to one aspect of the present invention, the...
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7543120 |
Processor and data processing system employing a variable store gather window
A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue...
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7529889 |
Data processing apparatus and method for performing a cache lookup in an energy efficient manner
A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing...
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7523266 |
Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level
One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor....
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7523261 |
Method and circuit arrangement for adapting a program to suit a buffer store
A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a...
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7500066 |
Method and apparatus for sharing instruction memory among a plurality of processors
A multiprocessing apparatus includes a memory and a plurality (M) of processors coupled to share the memory. Access to the memory is time-division multiplexed among the plurality of processors. In...
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7493621 |
Context switch data prefetching in multithreaded computer
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
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7493447 |
System and method for caching sequential programs
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
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7478199 |
Cache coloring based on dynamic function flow
A method of performing cache coloring includes the steps of generating function strength information in response to a dynamic function flow representing a sequence in which a plurality of functions...
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7478198 |
Multithreaded clustered microarchitecture with dynamic back-end assignment
A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an...
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7469332 |
Systems and methods for adaptively mapping an instruction cache
Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for...
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7461205 |
Performing useful computations while waiting for a line in a system with a software implemented cache
Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes...
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7456835 |
Register based queuing for texture requests
A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture...
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7454570 |
Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor
A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of...
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7437537 |
Methods and apparatus for predicting unaligned memory access
In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the...
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7437512 |
Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the...
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7427990 |
Data replacement method and circuit for motion prediction cache
A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the...
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7426626 |
TLB lock indicator
A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The...
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7426612 |
Methods and apparatus for enforcing instruction-cache coherence
Methods and apparatus for enforcing instruction-cache coherence are described herein. In an example method, a memory region of an instruction cache is initialized to form an initialized memory...
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7418552 |
Memory disambiguation for large instruction windows
A memory disambiguation apparatus includes a store queue, a store forwarding buffer, and a version count buffer. The store queue includes an entry for each store instruction in the instruction...
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7414517 |
Radio frequency identification transponder
A radio frequency identification transponder includes a power supply and a dynamic memory array that stores data. When power from the power supply ceases, the data in the dynamic memory array is...
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7406569 |
Instruction cache way prediction for jump targets
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
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7404042 |
Handling cache miss in an instruction crossing a cache line boundary
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process...
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7401184 |
Matching memory transactions to cache line boundaries
In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to...
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7389385 |
Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis
Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with...
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7386670 |
Processing of self-modifying code in multi-address-space and multi-processor systems
A method and system of storing to an instruction stream with a multiprocessor or multiple-address-space system is disclosed. A central processing unit may cache instructions in a cache from a page...
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7383403 |
Concurrent bypass to instruction buffers in a fine grain multithreaded processor
In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit...
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7366885 |
Method for optimizing loop control of microcoded instructions
A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a...
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7366875 |
Method and apparatus for an efficient multi-path trace cache design
A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant...
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7366851 |
Processor, method, and data processing system employing a variable store gather window
A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue...
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7363468 |
Load address dependency mechanism system and method in a high frequency, low power processor system
The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At...
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7363428 |
Microprocessor with hot routine memory and method of operation
Information designated as a hot routine by an application program is stored in a hot routine memory of the microprocessor system. A processor requests information, and a controller controls the hot...
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7356456 |
Computer storage exception handing apparatus and method for virtual hardware system
In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples,...
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7355601 |
System and method for transfer of data between processors using a locked set, head and tail pointers
A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task...
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7353513 |
Method and apparatus for establishing a bound on the effect of task interference in a cache memory
A method and apparatus are disclosed for establishing a bound on the effect of task interference in an instruction cache shared by multiple tasks. The bound established by the present invention is...
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7353445 |
Cache error handling in a multithreaded/multi-core processor
In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error...
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7353337 |
Reducing cache effects of certain code pieces
Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since...
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7346741 |
Memory latency of processors with configurable stride based pre-fetching technique
A method and apparatus for retrieving instructions to be processed by a microprocessor is provided. By pre-fetching instructions in anticipation of being requested, instead of waiting for the...
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7346737 |
Cache system having branch target address cache
A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The...
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