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5696935 Multiported cache and systems  
A cache memory is provided with a plurality of address ports and a corresponding plurality of tag ports for use with multiple pipes in a pipelined system. One of the address ports is dedicated to...
5659706 Vector/scalar processor with simultaneous processing and instruction cache filling  
The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector...
5651134 Method for configuring a cache memory to store only data, only code, or code and data based on the operating characteristics of the application program  
A method for configuring a cache memory which configures a bus controller to select either code only, data only, or code and data for storage in the cache memory. The configuration method includes...
5649154 Cache memory system having secondary cache integrated with primary cache for use with VLSI circuits  
A cache memory system with a secondary cache integrated with a direct mapped primary cache in a single structure preferably constructed on a VLSI chip. The secondary cache uses the same output data...
5630075 Write combining buffer for sequentially addressed partial line operations originating from a single instruction  
A microprocessor having a bus for the transmission of data, an execution unit for processing data and instructions, a memory for storing data and instructions, and a write combining buffer for...
5619663 Computer instruction prefetch system  
An instruction prefetch system for a digital processor, and in particular a microcontroller which includes the prefetch system and instruction queue normally provided as part of the instruction...
5594884 Cache memory system having a plurality of ports  
An instruction cache and a data cache are formed with a 2-port structure, the first port of the instruction cache is exclusively used for readout of the contiguous instruction, and the second port...
5586293 Real time cache implemented by on-chip memory having standard and cache operating modes  
An integrated circuit chip includes a processor (4) and a memory (10) coupled by data and address buses (PAB, PDB). The memory is switchable between a first, standard, mode of operation in which a...
5586296 Cache control system and method for selectively performing a non-cache access for instruction data depending on memory line access frequency  
A cache control system and method for operating a computer system which is capable of executing cached and non-cached memory accesses. The cache control system includes a frequency value store for...
5586294 Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer  
A read buffering system employs FIFOs to hold sequential read data for a number of data streams being fetched by a computer. When the system sees a read command from the CPU, it stores an...
5586295 Combination prefetch buffer and instruction cache  
A cache memory system features a combination instruction cache and prefetch buffer, which obviates any requirement for a bus interconnecting the cache and buffer and which also effectively allows...
5561782 Pipelined cache system having low effective latency for nonsequential accesses  
A method and apparatus for reducing the effective latency for nonsequential memory accesses is disclosed. An improved cache includes a multi-stage pipelined cache that provides at least one cache...
5553254 Instruction cache access and prefetch process controlled by a predicted instruction-path mechanism  
A first-in-first-out queue is used to manage instruction sequence execution from an instruction cache in a computer processor. Fields are provided in the queue element structure for not only...
5537553 Method of and apparatus for bus control and data processor  
In a processor having a central processing unit, an instruction cache and a data cache, a bus controller is provided for controlling giving and receiving of a signal between internal instruction...
5537571 Control device for a buffer memory with reconfigurable partitioning  
Control device for a buffer memory which distinguishes information of the "instruction" type and information of the "data" type, and which replaces stored information with current information...
5532947 Combined decoder/adder circuit which provides improved access speed to a cache  
The present invention is directed toward an combined decoder/adder circuit which provides faster access to a cache in a microprocessor than implementations which include an adder circuit which is...
5515518 Two-level branch prediction cache  
AN improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a...
5511178 Cache control system equipped with a loop lock indicator for indicating the presence and/or absence of an instruction in a feedback loop section  
In a cache memory 20, there exist a plurality of cache lines 201, each of which is equipped with a loop lock L for indicating that an instruction is present in a feedback loop section. The states...
5493667 Apparatus and method for an instruction cache locking scheme  
An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two...
5493664 Microcomputer that transfers address and control to a debugging routine when an input address is a breakpoint address and a user accessible register for signalling if the breakpoint address is from the cache memory or a main memory  
A processor according to the present invention includes a user-accessible 1 bit register for indicating, upon instruction breaking or data breaking occurring, whether any instruction or data to be...
5488710 Cache memory and data processor including instruction length decoding circuitry for simultaneously decoding a plurality of variable length instructions  
A cache memory, and a data processor including the cache memory, for processing at least one variable length instruction from a memory and outputting processed information to a control unit, such...
5450561 Cache miss prediction method and apparatus for use with a paged main memory in a data processing system  
In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called...
5404469 Multi-threaded microprocessor architecture utilizing static interleaving  
A static interleaving technique solves the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture. In the static interleaving technique, each...
5404466 Apparatus and method to set and reset a pipeline instruction execution control unit for sequential execution of an instruction interval  
An execution control system for use in a pipeline instruction execution control type information processing device, wherein an instruction interval is executed sequentially after completion of a...
5381533 Dynamic flow instruction cache memory organized around trace segments independent of virtual address line  
An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory...
5371865 Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand  
A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory...
5335330 Information processing apparatus with optimization programming  
An information processing apparatus wherein a plurality of instructions are checked in an instruction buffer circuit, the plurality of instructions excluding instructions being executed. If there...
5301295 Data processor apparatus and method with selective caching of instructions  
The effective capacity of an instruction cache in a digital signal processor with a modified HARVARD architecture is enhanced by decoding a current instruction to be executed to determine whether...
5249286 Selectively locking memory locations within a microprocessor's on-chip cache  
A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and...
5233694 Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously  
The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A...
5210842 Data processor having instruction varied set associative cache boundary accessing  
A data processor having an instruction varied set associative cache boundary access capability provides reduced power consumption and maintains data processor performance. Queued data processor...
5201052 System for transferring first and second ring information from program status word register and store buffer  
A microprocessor provides a CPU to execute a program and a register to store a program status word indicative of a status of the program being executed by the CPU. The program status word includes...
5187793 Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache  
An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions...
5179680 Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus  
A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each...
5170476 Data processor having a deferred cache load  
A data processing system is provided having a secondary cache for performing a deferred cache load. The data processing system has a pipelined integer unit which uses an instruction prefetch unit...
5161217 Buffered address stack register with parallel input registers and overflow protection  
A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to...
5134562 Fifo register device adaptively changing a stage number in dependency on a bus cycle  
In a first-in-first-out register device positioned intermediately between an address calculation circuit and an operation execution circuit, both of which are individually operable in pipeline...
5113515 Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer  
An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction...
5027270 Processor controlled interface with instruction streaming  
A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing...
4933837 Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories  
Methods and apparatus are set forth for optimizing the performance of instruction processors using an instruction cache memory in combination with a sequential transfer main memory. According to...
4930102 Dynamic activity-creating data-driven computer architecture  
A computer architecture wherein data inputs causes the dynamic creation of appropriate activities employing stored functions as necessary to accomplish the desired end result for the data. The...
4912626 Hit predictive cache memory  
A cache memory when receiving an operand read request and the operand address from a central processing unit responds with a signal indicative of an operand being available in the cache memory...
4626988 Instruction fetch look-aside buffer with loop mode control  
A instruction fetch look-aside buffer with a loop mode control provides for reduced storage contention by storing a program loop in a look-aside buffer during normal mode operations. When the loop...
4607329 Circuit arrangement for the temporary storage of instruction words  
For the temporary storage of instruction words read out of an instruction memory, an arrangement is used of one of a plurality of buffer memories (20 to 23) which are addressed for writing in and...
4566063 Data processor which can repeat the execution of instruction loops with minimal instruction fetches  
A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during...
4442488 Instruction cache memory system  
A memory system includes a high-speed, multi-region instruction cache, each region of which stores a variable number of instructions received from a main data memory said instructions forming part...
4095269 Data processing system having a high speed buffer memory  
A data processing system has a main memory, a buffer memory, an instruction control unit, and an arithmetic unit. The data processing system also includes a register for storing an address for...
4040033 Microprogrammable data processor with a microprogram buffer memory  
A control unit for a processor, which can be controlled by microprograms, in a data processing system utilizes a microprogram memory into which recordings can be made (writable control memory),...
3949376 Data processing apparatus having high speed slave store and multi-word instruction buffer  
Instructions are written in multi-word blocks into an instruction buffer from a slave store, and then scanned sequentially. The instruction buffer is unequally divided, a first part of a block...
3614747 INSTRUCTION BUFFER SYSTEM  
An instruction buffer for electronic computer systems, mainly comprising a pair of groups of registers in which instructions read out from the memory unit are stored and a control unit for...
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