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7669011 Method and apparatus for detecting and tracking private pages in a shared memory multiprocessor  
A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory...
7644237 Method and apparatus for global ordering to insure latency independent coherence  
A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment...
7613882 Fast invalidation for cache coherency in distributed shared memory system  
An example embodiment of the present invention provides processes relating to a cache coherence protocol for distributed shared memory. In one process, a DSM-management chip receives a request to...
7552288 Selectively inclusive cache architecture  
In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the...
7529799 Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system  
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
7523260 Propagating data using mirrored lock caches  
A method, processing node, and computer readable medium for propagating data using mirrored lock caches are disclosed. The method includes coupling a first mirrored lock cache associated with a...
7493621 Context switch data prefetching in multithreaded computer  
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
7487321 Method and system for memory leak detection  
Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit...
7444474 Determining the presence of a virtual address in a cache  
An information carrier medium containing software that, when executed by a processor, causes the processor to receive status information from circuit logic that collects the status information from...
7421538 Storage control apparatus and control method thereof  
A storage control apparatus controls physical disks according to the host access using a pair of controllers, while mirroring processing is decreased when data is written to a cache memory and...
7404046 Cache memory, processing unit, data processing system and method for filtering snooped operations  
A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache...
7370155 Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response  
A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor...
7305523 Cache memory direct intervention  
A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request...
7305522 Victim cache using direct intervention  
A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request...
7293142 Memory leak detection system and method using contingency analysis  
Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit...
7287122 Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing  
A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache,...
7266644 Storage system and file-reference method of remote-site storage system  
A storage system conducting remote copy functions such that, when data is updated at a local site, contents of the update can be referred to in real time by storage at a remote site. A disk-control...
7222220 Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices  
A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the...
7197602 Multiple cache communication and uncacheable objects  
The invention provides a method and system for operating multiple communicating caches. Between caches, unnecessary transmission of repeated information is substantially reduced. Each cache...
7159077 Direct processor cache access within a system having a coherent multi-processor protocol  
A computer system has a plurality of processors in a multiprocessor system with each processor associated with a cache memory. The cache traffic is monitored by the respective processors to...
7130961 Disk controller and method of controlling the cache  
To execute cache data identity control between disk controllers in plural disk controllers provided with each cache. To prevent a trouble from being propagated to another disk controller even if...
7120755 Transfer of cache lines on-chip between processing cores in a multi-core system  
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific...
7076613 Cache line pre-load and pre-own based on cache coherence speculation  
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor...
7055003 Data cache scrub mechanism for large L2/L3 data cache structures  
A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the...
7032078 Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols  
A multiprocessor computer system to selectively transmit address transactions using a broadcast mode or a point-to-point mode. Either a directory-based coherency protocol or a broadcast snooping...
6993633 Computer system utilizing speculative read requests to cache memory  
A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data...
6970982 Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions  
A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of...
6963953 Cache device controlling a state of a corresponding cache memory according to a predetermined protocol  
It assumes that “SO” represents a state, in which that data in a responsible region storing the data to be accessed most frequently by the corresponding processor is updated in a cache memory...
6950908 Speculative cache memory control method and multi-processor system  
The processors # 0 to # 3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor # 1 that executes a thread updates the self-cache memory # 1, if...
6889293 Directory-based prediction methods and apparatus for shared-memory multiprocessor systems  
A set of predicted readers are determined for a data block subject to a write request in a shared-memory multiprocessor system by first determining a current set of readers of the data block, and...
6886162 High speed methods for maintaining a summary of thread activity for multiprocessor computer systems  
A high-speed method for maintaining a summary of thread activity reduces the number of remote-memory operations for an n processor, multiple node computer system from n 2 to (2n−1) operations....
6877067 Shared cache memory replacement control method and apparatus  
In a multiprocessor system in which a plurality of processors share an n-way set-associative cache memory, a plurality of ways of the cache memory are divided into groups, one group for each...
6871268 Methods and systems for distributed caching in presence of updates and in accordance with holding times  
Techniques for improved cache management including cache replacement are provided. In one aspect, a distributed caching technique of the invention comprises the use of a central cache and one or...
6868482 Method and apparatus for parallel store-in second level caching  
Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the...
6865645 Program store compare handling between instruction and operand caches  
A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction...
6836826 Multilevel cache system and method having a merged tag array to store tags for multiple data arrays  
A multilevel cache system and method. A first data array and a second data array are coupled to a merged tag array. The merged tag array stores tags for both the first data array and second data...
6826656 Reducing power in a snooping cache based multiprocessor environment  
A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache...
6820182 Support for exhaustion recovery in a data processing system with memory mirroring  
A memory exhaustion condition is handled in a data processing system having first and second regions of physical memory. The memory exhaustion condition is detected while the second region is...
6807606 Distributed execution coordination for web caching with dynamic content  
A system and method are disclosed, according to which, the responsiveness of client/server-based distributed web applications operating in an object-oriented environment may be improved by...
6801984 Imprecise snooping based invalidation mechanism  
A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided...
6775749 System and method for performing a speculative cache fill  
A computer system may include several caches that are each coupled to receive data from a shared memory. A cache coherency mechanism may be configured to receive a cache fill request, and in...
6763436 Redundant data storage and data recovery system  
A data replication system is disclosed in which replication functionalities between a host computer, an interconnecting computer network, and a plurality of storage devices are separated into host...
6754782 Decentralized global coherency management in a multi-node computer system  
A non-uniform memory access (NUMA) computer system includes a first node and a second node coupled by a node interconnect. The second node includes a local interconnect, a node controller coupled...
6751705 Cache line converter  
A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and...
6738870 High speed remote storage controller  
A high speed remote storage controller system for a computer system has cluster nodes of symmetric multiprocessors. A plurality of clusters of symmetric multiprocessors each of has a plurality of...
6738871 Method for deadlock avoidance in a cluster environment  
A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces...
6738872 Clustered computer system with deadlock avoidance  
A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces...
6711662 Multiprocessor cache coherence management  
A shared-memory system includes processing modules communicating with each other through a network. Each of the processing modules includes a processor, a cache, and a memory unit that is locally...
6697849 System and method for caching JavaServer Pages™ responses  
System and method for caching JavaServer Page™ (JSP) component responses. The JSP components may be components that execute on an application server that supports networked applications, such as...
6687795 Data processing system and method of communication that reduce latency of write transactions subject to retry  
A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry...
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