Matches 1 - 50 out of 199 1 2 3 4 >
Match Document Document Title
7602758 Method to obtain friendly names for Bluetooth devices  
A method and apparatus to decrease the amount of time it takes to obtain friendly names of Bluetooth devices is presented. A name server caches friendly names for devices that it has acquired from...
7574500 Establishing a cache expiration time to be associated with newly generated output by determining module- specific cache expiration times for a plurality of processing modules  
Providing an input-dependent output is disclosed. A received message is processed to determine if a previously cached output exists for the received message. If a previously cached output is found,...
7552283 Efficient memory hierarchy management  
In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for...
7543127 Computer system  
A technology for allowing the smooth acquisition of required data when a processor switches working modes in a computer system is provided. According to one aspect of the present invention, the...
7529889 Data processing apparatus and method for performing a cache lookup in an energy efficient manner  
A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing...
7493621 Context switch data prefetching in multithreaded computer  
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
7493447 System and method for caching sequential programs  
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
7478199 Cache coloring based on dynamic function flow  
A method of performing cache coloring includes the steps of generating function strength information in response to a dynamic function flow representing a sequence in which a plurality of functions...
7461205 Performing useful computations while waiting for a line in a system with a software implemented cache  
Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes...
7406569 Instruction cache way prediction for jump targets  
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
7404042 Handling cache miss in an instruction crossing a cache line boundary  
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process...
7395380 Selective snooping by snoop masters to locate updated data  
A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less...
7388876 Method and system for transmitting data in two steps by using data storage provided in data transmission equipment in network  
In a method for transmitting data from a first node to a second node through an interlinking network including data transmission equipments: the data is transmitted from the first node to one of...
7360024 Multi-port integrated cache  
A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a...
7360022 Synchronizing an instruction cache and a data cache on demand  
In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a...
7340588 Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code  
This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code...
7336623 Peer-to-peer cloud-split detection and repair methods  
A method for detecting and repairing cloud splits in a distributed system such as a peer-to-peer (P2P) system is presented. Nodes in a cloud maintain a multilevel cache of entries for a subset of...
7334086 Advanced processor with system on a chip interconnect technology  
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and...
7330954 Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices  
Briefly, in accordance with an embodiment of the invention, a method to store information is provided, wherein the method includes generating a storage parameter to store information, wherein the...
7328433 Methods and apparatus for reducing memory latency in a software application  
Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce...
7310709 Method and apparatus for primary cache tag error handling  
A method and apparatus is disclosed for maintaining coherency between a primary cache and a secondary cache in a directory-based cache system. Upon identifying a parity error in the primary cache,...
7249352 Apparatus and method for removing elements from a linked list  
Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one...
7228410 Network interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic  
Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode...
7228409 Networking interface sharing methods and apparatuses that support kernel mode data traffic and user mode data traffic  
Methods and apparatuses are provided that allow kernel mode data traffic and user mode data traffic to share a common network communication port. One apparatus includes user mode logic, kernel mode...
7203798 Data memory cache unit and data memory cache system  
A data memory cache unit is provided which is capable of heightening the speed of memory access. The cache unit 117 executes reading and writing of data in a 16-byte width line unit in a main...
7142541 Determining routing information for an information packet in accordance with a destination address and a device address  
According to some embodiments, routing information for an information packet is determined in accordance with a destination address and a device address.
7133968 Method and apparatus for resolving additional load misses in a single pipeline processor under stalls of instructions not accessing memory-mapped I/O regions  
An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor...
7127561 Coherency techniques for suspending execution of a thread until a specified memory access occurs  
Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having...
7114034 Caching of dynamic arrays  
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment,...
7110382 Method to obtain friendly names for Bluetooth devices  
A method and apparatus to decrease the amount of time it takes to obtain friendly names of Bluetooth devices is presented. A name server caches friendly names for devices that it has acquired from...
7096318 Content-addressable (associative) memory devices  
A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel...
7089376 Reducing snoop response time for snoopers without copies of requested data via snoop filtering  
In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering...
7065612 Processor having cache structure and cache management method for elevating operation speed  
A processor having a cache memory structure which improves an operation speed of the processor and a method of managing cache memory of the processor are provided. The cache memory is divided into...
7062607 Filtering basic instruction segments in a processor front-end for power conservation  
Power conservation may be achieved in a front end system by disabling a segment builder unless program flow indicates a sufficient likelihood of segment reuse. Power normally spent in collecting...
7024524 Semiconductor storage  
It is an object to obtain a semiconductor storage having a 1—chip structure which can be simultaneously accessed to memory cells present in different memory cell arrays. A 1-port memory cell...
7024523 Host adapter integrated data FIFO and data cache and method for improved host adapter sourcing latency  
A host adapter, which interfaces two I/O buses, caches data transferred from one I/O bus to another I/O bus in a data first-in-first-out (FIFO)/caching memory. In addition, when a target device on...
6981103 Cache memory control apparatus and processor  
A cache memory control apparatus ( 20 ) that may control a cache memory ( 100 ) has been disclosed. Cache memory control apparatus ( 20 ) may include a control section ( 21 ). When a cache miss...
6961819 Method and apparatus for redirection of operations between interfaces  
A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the...
6920543 Method and apparatus for performing distributed processing of program code  
A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which...
6871264 System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits  
A processor integrated circuit capable of executing more than one instruction stream has two or more processors. Each processor accesses instructions and data through a cache controller. There are...
6865645 Program store compare handling between instruction and operand caches  
A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction...
6862675 Microprocessor and device including memory units with different physical addresses  
A main memory and a higher-speed local memory are externally connected to a microprocessor. The entire load module is developed in the main memory. A part or all of the instruction codes in the...
6848035 Semiconductor device with multi-bank DRAM and cache memory  
A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM...
6836828 Instruction cache apparatus and method capable of increasing a instruction hit rate and improving instruction access efficiency  
The present invention provides an instruction cache apparatus and method using the instruction read buffer. The apparatus comprises an instruction hit analysis unit, an instruction read buffer, a...
6829698 Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction  
A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor...
6816943 Scratch pad memories  
A processing system is disclosed. The processing system includes at least one cache and at least one scratch pad memory. The system also includes a processor for accessing the at least one cache...
6804799 Using type bits to track storage of ECC and predecode bits in a level two cache  
A microprocessor configured to store victimized instruction and data bytes is disclosed. In one embodiment, the microprocessor includes a predecode unit, and instruction cache, a data cache, and a...
6779102 Data processor capable of executing an instruction that makes a cache memory ineffective  
A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the...
6751704 Dual-L2 processor subsystem architecture for networking system  
A method for providing a memory scheme in computer architectures in an efficient and cost effective manner. A processor is configured with access to dual-L2 caches, preferably configured to cache...
6738884 Method and apparatus for processing data with semaphores  
A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which...
Matches 1 - 50 out of 199 1 2 3 4 >