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9043555 Single instance buffer cache method and system  
Provided is a method and system for reducing duplicate buffers in buffer cache associated with a storage device. Reducing buffer duplication in a buffer cache includes accessing a file reference...
9043554 Cache policies for uncacheable memory requests  
Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the...
9037800 Speculative copying of data from main buffer cache to solid-state secondary cache of a storage server  
A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache,...
9026731 Memory scheduling for RAM caches based on tag caching  
A system, method and computer program product to store tag blocks in a tag buffer in order to provide early row-buffer miss detection, early page closing, and reductions in tag block transfers. A...
9026741 System and method for warming cache  
A method, computer program product, and computing system for receiving an indication of a cold cache event within a storage system. The storage system includes a multi-tiered data array including...
9021206 Use of cache statistics to ration cache hierarchy access  
A method, system and program are provided for controlling access to a specified cache level in a cache hierarchy in a multiprocessor system by evaluating cache statistics for a specified...
9009415 Memory system including a spiral cache  
An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by...
9009408 Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system  
This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache line, merges the write data with data...
9003125 Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index  
A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the...
9003122 Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence  
This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in...
9003099 Disc device provided with primary and secondary caches  
In a disc device according to the present invention, when a controller 2 abandons a block from a cache memory 4 used as a primary cache, it is determined whether or not the number of readings of...
8996812 Write-back coherency data cache for resolving read/write conflicts  
A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is...
8990501 Multiple cluster processor  
A multiple processor system is disclosed. The processor system includes a first cluster including a first plurality of processors is associated with a first cluster cache, a second cluster...
8990502 Write cache structure in a storage system  
A method of writing data units to a storage device. The data units are cached in a first level cache sorted by logical address. A group (Gj) of sorted data units is transferred from the first...
8990503 Monitoring multiple memory locations for targeted stores in a shared-memory multiprocessor  
A system and method for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second...
8990506 Replacing cache lines in a cache memory based at least in part on cache coherency state information  
In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the...
8984255 Processing device with address translation probing and methods  
A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of...
8982140 Hierarchical memory addressing  
One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location...
8977823 Store buffer for transactional memory  
Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a...
8972664 Multilevel cache hierarchy for finding a cache line on a remote node  
Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests...
8972663 Broadcast cache coherence on partially-ordered network  
A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave...
8972661 Dynamically adjusted threshold for population of secondary cache  
The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data...
8972662 Dynamically adjusted threshold for population of secondary cache  
The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data...
8966178 Populating a first stride of tracks from a first cache to write to a second stride in a second cache  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
8966181 Memory hierarchy with non-volatile filter and victim caches  
Various embodiments of the present invention are generally directed to an apparatus and method for non-volatile caching of data in a memory hierarchy of a data storage device. In accordance with...
8959279 Populating a first stride of tracks from a first cache to write to a second stride in a second cache  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
8953354 Semiconductor memory device and method of driving semiconductor memory device  
A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural...
8949541 Techniques for evicting dirty data from a cache using a notification sorter and count thresholds  
A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame...
8949538 Interface device accessing a stack of memory dice and a solid state disk  
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is...
8949540 Lateral castout (LCO) of victim cache line in data-invalid state  
A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect...
8949539 Conditional load and store in a shared memory  
A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of...
8949837 Assist thread for injecting cache memory in a microprocessor  
A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system...
8943272 Variable cache line size management  
According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line...
8935479 Adaptive cache promotions in a two level caching system  
Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is...
8935478 Variable cache line size management  
According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the...
8930624 Adaptive cache promotions in a two level caching system  
Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is...
8924647 Dynamic selection of data replacement protocol for multi-level cache  
An improved technique for managing data replacement in a multi-level cache dynamically selects a data replacement protocol from among multiple candidates based on which data replacement protocol...
8924646 Methods for managing data movement and destaging data in a multi-level cache system utilizing threshold values and metadata  
A method for managing data movement in a multi-level cache system includes selecting at least one outgoing data block from a primary cache when an unallocated space of the primary cache has...
8922565 System and method for using a secondary processor in a graphics system  
A system, method and apparatus are disclosed, in which a processing unit is configured to perform secondary processing on graphics pipeline data outside the graphics pipeline, with the output from...
8924652 Simultaneous eviction and cleaning operations in a cache  
Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the...
8924623 Method for managing multi-layered data structures in a pipelined memory architecture  
A method for managing multi-layered data structures in a pipelined memory architecture, comprising the steps of: —providing a multi-level data structure where each level corresponds to a memory...
8918587 Multilevel cache hierarchy for finding a cache line on a remote node  
Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests...
8909868 Quality of service control method for storage system  
A method and a system for controlling quality of service of a storage system, and a storage system. The method includes: collecting information about processing capabilities of the hard disks in...
8909872 Computer system with coherent interconnection  
A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is...
8904110 Distributed user controlled multilevel block and global cache coherence with accurate completion status  
This invention permits user controlled cache coherence operations with the flexibility to do these operations on all levels of cache together or each level independently. In the case of an all...
8898431 Multi-path network  
The present invention provides a multi-path network for use in a bridge, switch, router, hub or the like, comprising a plurality of network ports adapted for connection with one or more devices,...
8892822 Selectively dropping prefetch requests based on prefetch accuracy information  
The disclosed embodiments relate to a system that selectively drops a prefetch request at a cache. During operation, the system receives the prefetch request at the cache. Next, the system...
8880807 Bounding box prefetcher  
A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher...
8874848 Intelligence for controlling virtual storage appliance storage allocation  
A change in workload characteristics detected at one tier of a multi-tiered cache is communicated to another tier of the multi-tiered cache. Multiple caching elements exist at different tiers, and...
8874847 Active memory processor system  
In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation...