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7616470 |
Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom
A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement...
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7610449 |
Apparatus and method for saving power in a trace cache
A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional...
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7606994 |
Cache memory system including a partially hashed index
In one embodiment, a cache memory system includes a cache memory coupled to a cache controller. The cache memory controller may receive an address and generate an index value corresponding to the...
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7606978 |
Multi-node computer system implementing global access state dependent transactions
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to...
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7603521 |
Prioritizing caches having a common cache level
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from...
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7603439 |
System for tiered distribution in a content delivery network
A tiered distribution service is provided in a content delivery network (CDN) having a set of surrogate origin (namely, “edge”) servers organized into regions and that provide content delivery...
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7596662 |
Selective storage of data in levels of a cache memory
In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the...
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7596661 |
Processing modules with multilevel cache architecture
A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at...
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7590868 |
Method and apparatus for managing encrypted data on a computer readable medium
A method and apparatus for managing encrypted data on a computer readable medium wherein an encryption key is determined for a received quantum of data. The quantum of data is encrypted according...
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7589738 |
Cache memory management system and method
A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The...
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7581065 |
Low locality-of-reference support in a multi-level cache hierachy
A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains...
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7571291 |
Information processing system, primary storage device, and computer readable recording medium recorded thereon logical volume restoring program
In a hierarchical storage system, a primary storage device interposed between a secondary storage device and a data processing apparatus has a restoring unit. When at least two current storage...
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7571284 |
Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is...
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7571188 |
Cache abstraction for modeling database performance
A method for modeling a database management system involving receiving a query, computing a hit rate value associated with a cache, wherein the hit rate value is computed using a counter group,...
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7565490 |
Out of order graphics L2 cache
Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that...
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7562190 |
Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture
A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability...
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7554978 |
System for accessing content-addressable memory in packet processor
A system for accessing a content-addressable memory in a packet processing system is described. A register holds a data element having a key field. Logic derives a value of the key responsive to 1)...
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7552288 |
Selectively inclusive cache architecture
In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the...
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7552287 |
Method and system of controlling a cache memory by interrupting prefetch request with a demand fetch request
A cache memory control unit that controls a cache memory comprises: a PF-PORT 22 and MI-PORT 21 that receive a prefetch request and demand fetch request issued from a primary cache; and a...
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7539819 |
Cache operations with hierarchy control
An improved approach to cache management is disclosed which may be implemented to provide fine-grained control over individual caches or subsets of a multi-level cache hierarchy. By selectively...
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7523158 |
System and method for partial page updates using a proxy element
A system and method for updating page content of a web page includes applying a partial page update from a content server to the page content through a proxy content element. This avoids having to...
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7519775 |
Enforcing memory-reference ordering requirements at the L2 cache level
One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein...
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7500065 |
Data processing system and method for efficient L3 cache directory management
A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state...
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7500049 |
Providing a backing store in user-level memory
In one embodiment, the present invention includes a method for requesting an allocation of memory to be a backing store for architectural state information of a processor and storing the...
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7496642 |
Adaptive vicinity prefetching for filesystem metadata
Network latencies are reduced by detecting a metadata access call for filesystem metadata contained in a filesystem node of remotely located filesystem. The metadata corresponding to the metadata...
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7493453 |
System, method and storage medium for prefetching via memory block tags
A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory...
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7493450 |
Method of triggering read cache pre-fetch to increase host read throughput
Exemplary systems and methods include pre-fetching data in response to a read cache hit. Various exemplary methods include priming a read cache with initial data, and triggering a read pre-fetch...
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7493446 |
System and method for completing full updates to entire cache lines stores with address-only bus operations
A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor...
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7490200 |
L2 cache controller with slice directory and unified cache structure
A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a...
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7484062 |
Cache injection semi-synchronous memory copy operation
A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a...
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7484044 |
Method and apparatus for joint cache coherency states in multi-interface caches
A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache...
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7475194 |
Apparatus for aging data in a cache
A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier...
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7475193 |
Separate data and coherency cache directories in a shared cache in a multiprocessor system
A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two...
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7475191 |
Processor, data processing system and method for synchronizing access to data in shared memory
A processing unit for a multiprocessor data processing system includes a processor core and a lower level cache including a reservation logic that records reservations of the processor core. The...
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7472225 |
Caching data
A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level...
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7472219 |
Data-storage apparatus, data-storage method and recording/reproducing system
A data-storage apparatus, a data-storage method and a recording/reproducing system are provided, which effectively use the time elapsing before data is transferred to be written in a recording...
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7467280 |
Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring...
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7461212 |
Non-inclusive cache system with simple control operation
A cache system includes a processing device operative to access a main memory device, a primary cache coupled to the processing device and accessible from the processing device at faster speed than...
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7461207 |
Methods and apparatus for controlling hierarchical cache memory
Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory...
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7454585 |
Efficient and flexible memory copy operation
A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a...
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7451295 |
Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues
One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests...
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7434007 |
Management of cache memories in a data processing apparatus
The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking...
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7428617 |
Cache memory and method to maintain cache-coherence between cache memory units
A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a...
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7428615 |
System and method for maintaining coherency and tracking validity in a cache hierarchy
A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy...
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7426611 |
Method and system for improved storage system performance using cloning of cached data
A method for improving storage system performance is disclosed. The method includes cloning information stored in a first unit of storage in a second unit of storage. The first unit of storage is...
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7426534 |
Method and system for caching message fragments using an expansion attribute in a fragment link tag
A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. After a message is received at a computing device that contains a cache management...
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7421562 |
Database system providing methodology for extended memory support
A database system providing methodology for extended memory support is described. In one embodiment, for example, a method is described for extended memory support in a database system having a...
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7412569 |
System and method to track changes in memory
Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary...
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7412565 |
Memory optimization for a computer system having a hibernation mode
A computer system that increases performance and reduces power consumption is described. Specifically, the system writes the contents of the system to a non-volatile memory cache before powering...
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7409524 |
System and method for responding to TLB misses
The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the...
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