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7620694 Early issue of transaction ID  
Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID...
7617363 Low latency message passing mechanism  
In one embodiment, a method is provided. The method of this embodiment provides detecting by a network controller a flush occurring on a host bus of a DM (“direct messaging”) packet to a memory...
7584327 Method and system for proximity caching in a multiple-core system  
Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as...
7581064 Utilizing cache information to manage memory access and cache utilization  
In a method of utilizing cache metadata to optimize memory access, cache metadata associated with a set of cache locations is inspected by software. The cache metadata is analyzed to determine...
7565474 Computer system using serial connect bus, and method for interconnecting a plurality of CPU using serial connect bus  
A computer system enable system operation by hiding the peculiarity of an upstream port of a switch in a computer system in which a plurality of CPU units are interconnected by a PCI Express...
7562190 Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture  
A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability...
7546353 Managed peer-to-peer applications, systems and methods for distributed data access and storage  
Applications, systems and methods for efficiently accessing data and controlling storage devices among multiple computers connected by a network. Upon receiving a request for access to data...
7536692 Thread-based engine cache partitioning  
In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled...
7526608 Methods and apparatus for providing a software implemented cache memory  
Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory...
7512737 Size based eviction implementation  
Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an...
7500031 Ring-based cache coherent bus  
Managing data traffic among three or more bus agents configured in a topological ring includes numbering each bus agent sequentially and injecting messages that include a binary polarity value from...
7404046 Cache memory, processing unit, data processing system and method for filtering snooped operations  
A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache...
7404041 Low complexity speculative multithreading system based on unmodified microprocessor core  
A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of...
7398360 Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors  
In one embodiment, a node comprises a plurality of processor cores, coherency control circuitry coupled to the plurality of processor cores, and at least one coherence unit coupled to the coherency...
7392346 Memory updater using a control array to defer memory operations  
A memory having multiple locations for data storage is updated by performing the following method. The memory locations are grouped into commonly accessible groups of one or more data locations....
7392345 Policy setting for client-side caching  
An improved method and system for client-side caching that transparently caches suitable network files for offline use. A cache mechanism in a network redirector transparently intercepts requests...
7350027 Architectural support for thread level speculative execution  
A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or...
7346738 Cache memory for a scalable information distribution system  
An information distribution system includes an interconnect and multiple data processing nodes coupled to the interconnect. Each data processing node includes mass storage and a cache. Each data...
7305523 Cache memory direct intervention  
A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request...
7305522 Victim cache using direct intervention  
A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request...
7246205 Software controlled dynamic push cache  
Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters...
7240143 Data access and address translation for retrieval of data amongst multiple interconnected access nodes  
A low-latency storage memory system is built from multiple memory units such as high-density random access memory. Multiple access ports provide access to memory units and send the resultant data...
7213107 Dedicated cache memory  
A method and apparatus for a dedicated cache memory are described. Under an embodiment of the invention, a cache memory includes a general-purpose sector and a dedicated sector. The general-purpose...
7181539 System and method for data synchronization  
Data is synchronized among multiple web servers, each of which is coupled to a common data server. Each web server retrieves a scheduled activation time from the data server. If the current time is...
7174431 Mechanism for resolving ambiguous invalidates in a computer system  
The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving...
7142541 Determining routing information for an information packet in accordance with a destination address and a device address  
According to some embodiments, routing information for an information packet is determined in accordance with a destination address and a device address.
7114156 System and method for processing multiple work flow requests from multiple users in a queuing system  
A system and method for generating a key list structure forming a queue of users' work flow requests in a queuing system such that many requests from a single user will not prevent processing of...
7086056 Processor unit for executing event processes in real time without causing process interference  
A processor unit executes a failure detection program for a vehicle. The failure detection program includes a first failure detection process of a high priority level, a second failure detection...
7076613 Cache line pre-load and pre-own based on cache coherence speculation  
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor...
7062606 Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events  
A multi-threaded embedded processor that includes an on-chip deterministic (e.g., scratch or locked cache) memory that persistently stores all instructions associated with one or more pre-selected...
7058770 Method and apparatus for controlling the recording of digital information, by using unit management table  
A recording area of a hard disk is managed by units. Each unit comprises physically continuous recording regions having predetermined size, and usage status of the unit is stored in an allocation...
6996678 Method and apparatus for randomized cache entry replacement  
A cache controller is disclosed. The cache controller includes potential replacement list, a plurality of valid bits and a number of counters. The potential replacement list includes a number of...
6996657 Apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system  
An apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer that may be configured to accumulate data received on a...
6986018 Method and apparatus for selecting cache and proxy policy  
A cache server includes a media serving engine that is capable of distributing media content. A cache engine is coupled to the media serving engine and capable of caching media content. A set of...
6973539 Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords  
A multiprocessor write-into-cache data processing system includes a feature for preventing hogging of ownership of a first gateword stored in the memory which governs access to a first common...
6963953 Cache device controlling a state of a corresponding cache memory according to a predetermined protocol  
It assumes that “SO” represents a state, in which that data in a responsible region storing the data to be accessed most frequently by the corresponding processor is updated in a cache memory...
6957313 Memory matrix and method of operating the same  
An apparatus and method for storing, manipulating, processing, and transferring data in a memory matrix ( 105 ). The matrix ( 105 ) includes a number of multi-ported memory devices ( 250 ) arranged...
6950908 Speculative cache memory control method and multi-processor system  
The processors # 0 to # 3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor # 1 that executes a thread updates the self-cache memory # 1, if...
6948010 Method and apparatus for efficiently moving portions of a memory block  
The present invention relates to a method and system for transferring portions of a memory block. A first data mover is configured with a first start address corresponding to a first portion of a...
6871268 Methods and systems for distributed caching in presence of updates and in accordance with holding times  
Techniques for improved cache management including cache replacement are provided. In one aspect, a distributed caching technique of the invention comprises the use of a central cache and one or...
6868483 Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment  
In a multiprocessor data processing system including: a main memory; at least first and second shared caches; a system bus coupling the main memory and the first and second shared caches; at least...
6865649 Method and apparatus for pre-fetching data during program execution  
A system and method for pre-fetching data. A computer program comprising multiple basic blocks is submitted to a processor for execution. Tables or other data structures are associated with some or...
6859864 Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line  
A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read...
6857052 Multi-processor system including a mode switching controller  
Any of the processors CPU 1 to CPUn turns the miss hit detecting signal line 5 to a low level upon detecting occurrence of a miss hit. In response, the mode switching controller 2 is notified...
6820186 System and method for building packets  
Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory....
6799247 Remote memory processor architecture  
A remote memory processor architecture which provides an embedded processor with access to a large off-chip memory space via a HOST processor bus. An on-chip embedded memory provides a cache memory...
6795905 Controlling accesses to isolated memory using a memory controller for isolated execution  
An access transaction generated by a processor is configured using a configuration storage containing a configuration setting. The processor has a normal execution mode and an isolated execution...
6766447 System and method of preventing speculative reading during memory initialization  
A method of initializing random access memory during a BIOS process executed by a processor that is configured to perform speculative reading. The ROM BIOS is modified such that speculative reading...
6766360 Caching mechanism for remote read-only data in a cache coherent non-uniform memory access (CCNUMA) architecture  
A computer network system for manipulating requests for shared data includes a plurality of groups and each group has a plurality of nodes and each node has a plurality of processors. The system...
6760811 Gateword acquisition in a multiprocessor write-into-cache environment  
In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors...
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